Low Power Design

The clock network consumes 20–40% of a chip's total dynamic power. Clock gating switches off the clock to flip-flop groups when their data won't change, eliminating switching power entirely for those registers.

ICG Cell Structure

An ICG (Integrated Clock Gating) cell is a latch + AND gate combination. The latch captures the enable signal on the clock low phase (preventing glitches), and the AND gate combines the latched enable with the clock. The output is a clean, glitch-free gated clock.

RTL Inference

Synthesis tools automatically infer ICG cells from common RTL patterns. The most reliable pattern is a register with an explicit enable:

// RTL — synthesis infers an ICG here
always @(posedge clk) begin
  if (data_valid) begin        // ← enable for ICG
    result_reg <= computed_result;
  end
end

// Do NOT write this (no ICG inferred):
always @(posedge clk) begin
  result_reg <= data_valid ? computed_result : result_reg;
end

UPF Clock Gating Pragma

In the UPF power intent file, you control ICG insertion strategy:

# UPF — set minimum bit-width for ICG insertion
set_clock_gating_style -minimum_bitwidth 4 \
                        -positive_edge_logic {integrated}
# Exclude a register from gating:
set_dont_touch_network [get_pins {u_reg/clk}]

Typical ICG area overhead is 5–10% (one ICG cell per gating group). The power saving easily justifies this: 20–40% reduction in total dynamic power for large designs.

Power gating cuts the power supply (VDD or VSS) to an entire logic block when it is idle, eliminating both dynamic and leakage power. It is the most powerful technique for standby power reduction.

Header vs Footer Topologies

Wake-up Sequence

The sleep/wake sequence must be carefully managed to avoid inrush current spikes and ensure correct state restoration:

// Power-down sequence (RTL pseudo-code)
1. assert isolation cells (block X-prop from powered-off domain)
2. retention FFs: pulse SAVE = 1 (state saved to balloon latches)
3. deassert sleep transistor enable → block powers off

// Wake-up sequence
1. assert sleep transistor enable → VVDD charges up
2. wait for VVDD_OK flag (power switch controller)
3. retention FFs: pulse RESTORE = 1 (state returns to main FF)
4. deassert isolation cells
5. release reset of block

UPF Power Domain Definition

create_power_domain PD_DSP -include_scope
create_supply_net  VVDD_DSP -domain PD_DSP
create_power_switch SW_DSP  -domain PD_DSP \
  -output_supply_port {vout VVDD_DSP}  \
  -input_supply_port  {vin VDD}        \
  -control_port       {sleep SLEEP_N}  \
  -on_state  {on  vin {!sleep}}        \
  -off_state {off     {sleep}}
set_retention PD_DSP -save_signal {SAVE posedge} -restore_signal {RESTORE posedge}

Dynamic Voltage and Frequency Scaling adjusts both supply voltage and clock frequency based on workload. Since P ∝ V²·f, reducing voltage from 1.0 V to 0.8 V saves 36% dynamic power — the largest single-variable lever available.

Voltage–Frequency Operating Points

Voltage Island Design

When different blocks run at different voltages simultaneously (e.g. GPU at 0.9 V, always-on controller at 1.0 V), the chip uses voltage islands separated by:

• Level shifters — convert logic levels crossing voltage boundaries (LS-LH and LS-HL variants)
• Isolation cells — clamp outputs of a powered-off domain to a safe value (0 or 1)
• Always-on buffers — in the low-voltage domain, powered from the always-on rail

Modern standard cell libraries offer cells at multiple threshold voltages. Higher V_t means less leakage but slower speed. The synthesis tool assigns cell flavours to maximise leakage reduction while meeting timing.

V_t Flavour Comparison

DC Shell — Leakage-Aware Synthesis

# Synopsys DC — enable multi-Vt leakage optimisation
compile_ultra -leakage_power

# Set leakage-to-dynamic trade-off weight (0=speed only, 10=leakage only)
set_leakage_optimization true
set power_cg_auto_identify true

# Swap non-critical cells to HVT post-route
swap_cell [get_cells -filter "is_critical==false"] -lib_cell HVT_AND2

Operand Isolation

When a functional unit (multiplier, FPU) is idle, its inputs often still toggle with garbage data, wasting power. Operand isolation inserts an AND or MUX gate to clamp inputs to zero when the unit is disabled:

// Without isolation — multiplier toggles even when idle
assign product = a * b;

// With operand isolation — zero inputs when mul_en=0
assign a_iso = mul_en ? a : '0;
assign b_iso = mul_en ? b : '0;
assign product = a_iso * b_iso;   // Synthesis recognises this pattern

Synthesis tools can insert operand isolation automatically from RTL enable signals when using set_operand_isolation pragmas or UPF.

RTL Low-Power Coding Guidelines

The Unified Power Format (UPF, IEEE 1801) is the industry-standard language for specifying power intent. It describes power domains, supply networks, isolation cells, level shifters, and retention strategies — allowing synthesis, simulation, and verification tools to apply low-power techniques consistently.

Key UPF Commands

Complete UPF Example — 2-Domain SoC

# Always-on domain (primary)
create_power_domain PD_TOP -include_scope

# Switchable DSP domain
create_power_domain PD_DSP
  add_elements -elements {u_dsp}

# Supply networks
create_supply_net VDD   -domain PD_TOP
create_supply_net VSS   -domain PD_TOP
create_supply_net VVDD  -domain PD_DSP

# Power switch (header topology)
create_power_switch PSW_DSP \
  -domain PD_DSP \
  -output_supply_port {vout VVDD} \
  -input_supply_port  {vin  VDD}  \
  -control_port       {sleep SLEEP_N} \
  -on_state  {on  vin {!sleep}} \
  -off_state {off     {sleep}}

# Isolation on DSP outputs (clamp to 0 when off)
set_isolation ISO_DSP \
  -domain PD_DSP -applies_to outputs \
  -clamp_value 0 \
  -isolation_power_net VDD \
  -isolation_ground_net VSS

# Level shifter (PD_TOP 1.0V → PD_DSP can run at 0.8V)
set_level_shifter LS_TO_DSP \
  -domain PD_DSP -applies_to inputs \
  -threshold 0.5

# Retention for DSP control registers
set_retention RET_DSP \
  -domain PD_DSP \
  -save_signal    {u_pmu/save    posedge} \
  -restore_signal {u_pmu/restore posedge}

# Power State Table
create_pst PST_MAIN -supplies {VDD VVDD}
add_pst_state active -pst PST_MAIN -state {VDD VVDD}
add_pst_state sleep  -pst PST_MAIN -state {VDD off}

UPF in the Design Flow

Body biasing adjusts the substrate voltage of transistors to tune their threshold voltage (V_t) at runtime. It gives designers a knob to trade speed against leakage after fabrication — without changing VDD or frequency.

Forward vs Reverse Body Bias

Adaptive Voltage Scaling (AVS)

AVS continuously monitors the critical path slack and adjusts VDD to maintain just enough margin — no more. Unlike fixed DVFS operating points, AVS adapts in real time to:

• Process variation — a fast-corner chip runs at lower VDD for the same frequency
• Temperature variation — hot silicon slows; AVS raises VDD to compensate
• Aging — as transistors degrade over years, AVS raises VDD to maintain Fmax

AVS is implemented by a critical path monitor (CPM) — a replica of the design's longest timing path in silicon. When the CPM triggers a near-miss, the power manager raises VDD by one step. This typically saves 5–15% compared to worst-case fixed VDD. ARM's Cortex-A series uses AVS in conjunction with DVFS for maximum energy efficiency.

Combined Strategy — Mobile SoC Example

// ARM Cortex-A55 (efficiency core) in sleep mode:
//   DVFS  : VDD = 0.55V, f = 200MHz
//   RBB   : V_body = −0.3V  → V_t raised 80mV → leakage ↓ 40%
//   Gating: all non-essential blocks power-gated
//   Result: 8mW total core power

// ARM Cortex-A78 (performance core) in turbo mode:
//   DVFS  : VDD = 1.05V, f = 3.2GHz
//   FBB   : V_body = +0.2V → V_t lowered 50mV → Fmax ↑ 8%
//   AVS   : monitors CPM, trims VDD ±25mV in real time
//   Result: 4W per core, maximum performance

These questions appear frequently in VLSI/RTL/Physical Design interviews at Qualcomm, Apple, NVIDIA, Intel, MediaTek, and semiconductor IP companies. Each answer is calibrated for senior engineer level.