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Free Course · 12 Days

Design for Testability (DFT)

From fault models and scan chains to ATPG, MBIST, JTAG, and tapeout sign-off. The complete DFT curriculum used in real VLSI product teams — with Verilog, waveforms, and interview Q&A every day.

By EcrioniX · Updated June 2026 · For VLSI engineers, DV engineers, and DFT job seekers
12
Days
6
Interview Q&A / Day
100%
Free
What You'll Learn

The Complete DFT Skill Set

Everything needed to contribute to DFT implementation, sign-off, and verification in an industry tape-out flow.

🔍
Fault models: stuck-at, transition, bridging, path delay — what each detects
🔗
Scan chain design: scan FFs, scan enable, shift vs capture modes
⚡
ATPG algorithms: D-algorithm, PODEM, FSIM — how patterns are generated
🗜️
Scan compression: EDT, X-compactor — reduce test time by 50–100×
🏃
At-speed testing: transition faults, LOC vs LOS, hold-time hazards
🔄
LBIST: PRPG, MISR, signature analysis for autonomous logic test
🧠
MBIST: March algorithms (March C-, March LR), memory fault models
🛠️
JTAG / IEEE 1149.1: TAP controller FSM, boundary scan cells, BSR
🔋
Low-power DFT: X-masking, power-aware ATPG, EDT with power constraints
📊
DFT sign-off: coverage targets, test escapes, DPPM, tester interface
🧩
DFT for chiplets: die-to-die testing, IEEE 1838, 3D IC test access
🎯
End-to-end DFT flow: from RTL constraints to ATE patterns + interview prep
Course Curriculum

12-Day DFT Roadmap

Each day builds on the previous. Start from Day 1 if you're new to DFT, or jump to any topic.

Day 01
Introduction to DFT — Why Test? Fault Models
Manufacturing defects, fault vs defect, stuck-at-0/1, transition, bridging, path delay faults. Fault coverage metrics and why 99% isn't good enough.
Fault ModelsStuck-atControllabilityObservability
Study Day 1 →
Day 02
Scan Design Fundamentals
Scan flip-flops, scan enable (SE) port, mux-scan vs clocked-scan, scan chain architecture, shift mode vs capture mode, scan-in/scan-out.
Scan FFShift ModeCapture ModeScan Chain
Study Day 2 →
Day 03
Scan Insertion & Compression (EDT)
Scan insertion flow (Tessent/TetraMAX), scan chain reordering, EDT compressor/decompressor architecture, X-tolerance, compression ratio calculation.
EDTX-compactorScan InsertionTessent
Study Day 3 →
Day 04
ATPG — Automatic Test Pattern Generation
D-algorithm, PODEM, FAN algorithm. Stuck-at fault ATPG, fault simulation, fault dropping, untestable faults. TetraMAX / Tessent ATPG flow.
ATPGD-algorithmPODEMFault Sim
Study Day 4 →
Day 05
At-Speed Testing — Transition Faults
Transition fault model, slow-to-rise / slow-to-fall, launch-on-capture (LOC) vs launch-on-shift (LOS), hold-time violations, small delay defects at advanced nodes.
Transition FaultLOCLOSAt-Speed
Study Day 5 →
Day 06
LBIST — Logic Built-In Self-Test
PRPG using LFSR, MISR response compaction, STUMPS architecture with phase shifter, aliasing probability, LBIST vs external ATPG, random-pattern-resistant faults.
LBISTPRPGMISRSTUMPS
Study Day 6 →
Day 07
MBIST — Memory Built-In Self-Test
Memory fault models (SAF, TF, CF, CFin), March C- and March LR algorithms, MBIST controller architecture, repair analysis, BISR, and redundancy schemes.
MBISTMarch C-Memory FaultsBISR
Study Day 7 →
Day 08
JTAG / Boundary Scan — IEEE 1149.1
TAP controller 16-state FSM, TDI/TDO/TCK/TMS/TRST signals, instruction register, boundary scan register (BSR), EXTEST/SAMPLE/BYPASS/IDCODE instructions explained.
JTAGTAP ControllerBSRIEEE 1149.1
Study Day 8 →
Day 09
DFT for Low Power
X-masking, power-aware ATPG, toggle rate analysis during scan shift, EDT with switching activity constraints, scan segmentation for power domains.
X-maskingPower ATPGScan PowerUPF
Coming soon
Day 10
DFT Metrics & Sign-off
Stuck-at coverage >99%, transition coverage targets, ATPG efficiency, DPPM (defective parts per million), test escapes, ATE interface, tester format conversion.
CoverageDPPMSign-offATE
Coming soon
Day 11
DFT for Advanced Nodes & Chiplets
IEEE P1838 3D test access, die-to-die testing, UCIe test modes, interconnect testing for chiplet packages, IJTAG (IEEE 1687), instrument network.
IEEE 1838Chiplet DFT3D ICIJTAG
Coming soon
Day 12
End-to-End DFT Flow + Interview Prep
Full DFT flow from RTL DFT constraints to ATE program. DFT review checklist, 30 DFT interview questions with expert answers, career paths in DFT.
DFT FlowInterview Q&AATEChecklist
Coming soon

Prerequisites