What You'll Learn
The Complete DFT Skill Set
Everything needed to contribute to DFT implementation, sign-off, and verification in an industry tape-out flow.
Fault models: stuck-at, transition, bridging, path delay — what each detects
Scan chain design: scan FFs, scan enable, shift vs capture modes
ATPG algorithms: D-algorithm, PODEM, FSIM — how patterns are generated
Scan compression: EDT, X-compactor — reduce test time by 50–100×
At-speed testing: transition faults, LOC vs LOS, hold-time hazards
LBIST: PRPG, MISR, signature analysis for autonomous logic test
MBIST: March algorithms (March C-, March LR), memory fault models
JTAG / IEEE 1149.1: TAP controller FSM, boundary scan cells, BSR
Low-power DFT: X-masking, power-aware ATPG, EDT with power constraints
DFT sign-off: coverage targets, test escapes, DPPM, tester interface
DFT for chiplets: die-to-die testing, IEEE 1838, 3D IC test access
End-to-end DFT flow: from RTL constraints to ATE patterns + interview prep
Course Curriculum
12-Day DFT Roadmap
Each day builds on the previous. Start from Day 1 if you're new to DFT, or jump to any topic.
Prerequisites
- Basic digital logic (gates, flip-flops, FSMs)
- Verilog / SystemVerilog basics
- Basic STA concepts (setup/hold time)
- No prior DFT knowledge needed