Home›Verification Series

25-Day Course

Verification Engineering
Tutorials

From Verilog testbench basics to full UVM architecture, SVA, formal verification, and DV interview prep. Structured, code-heavy, evergreen.

25

Tutorials

200+

Code examples

5

Tracks

Foundations UVM Core UVM Advanced Coverage & Formal Protocol & Interview

Track 1

Verification Foundations — Days 1–5

What is Design Verification?

DV vs design, simulation vs formal, functional vs structural verification, coverage-driven flow, role of a DV engineer in an ASIC team.

FundamentalsDV Flow

Verilog Testbench Basics

DUT instantiation, clock generation, reset sequencing, stimulus using initial blocks, $monitor/$display, file I/O, and self-checking testbench with $fatal.

VerilogTestbench

SystemVerilog for Verification

Interfaces, clocking blocks, programs, mailbox, semaphore, event, virtual interfaces — the SV constructs that are unique to verification and don't synthesize.

SystemVerilogInterface

SVA — SystemVerilog Assertions

Immediate vs concurrent assertions, property, sequence, ##, |=>, |->, $rose/$fell/$stable, disable iff, strong/weak operators, binding assertions to DUT.

Functional Coverage — Covergroup & Coverpoint

covergroup, coverpoint, bins (auto, explicit, range, wildcard), cross coverage, transition bins, iff guard, sample(), get_coverage() — with a full UART coverage model.

CoverageCovergroup

Track 2

UVM Core — Days 6–10

Introduction to UVM

What is UVM, uvm_component vs uvm_object, base class hierarchy, UVM phasing overview, `uvm_info/`uvm_error macros, naming conventions, running a minimal UVM test.

UVMBase Classes

UVM Testbench Architecture

Full UVM TB block diagram: test → env → agent (driver + monitor + sequencer) → scoreboard + coverage. How components connect via TLM ports and analysis ports.

UVM Sequences & seq_item

uvm_sequence_item with rand fields, uvm_sequence body(), start(), `uvm_do macros, virtual sequences for multi-agent coordination, p_sequencer, sequencer arbitration.

Sequencesseq_item

UVM Driver & Monitor

Driver get_next_item/item_done cycle, pin-level protocol driving, passive monitor sampling signals, analysis port broadcasting, clocking block usage in driver/monitor.

UVM Scoreboard & Checker

In-order vs out-of-order scoreboards, reference model, analysis imp, write() callback, queue-based matching, error counting, check_phase reporting with `uvm_error.

ScoreboardChecker

Track 3

UVM Advanced — Days 11–15

UVM RAL — Register Abstraction Layer

uvm_reg_block, uvm_reg, uvm_reg_field, frontdoor read/write, backdoor access with HDL paths, built-in register sequences (hw_reset, bit_bash, reg_access), adapter.

UVM Factory & Override

`uvm_component_utils, type vs instance override, set_type_override_by_type, factory.print() for debug, how override enables test-level component substitution without modifying env.

FactoryOverride

uvm_config_db::set/get, passing virtual interfaces from top module, configuring agent active/passive, propagating integer/string/object settings across the hierarchy.

config_dbInterface

UVM Phasing — build to report

All UVM phases: build_phase, connect_phase, start_of_simulation, run_phase (12 time-consuming fork-join sub-phases), extract, check, report, final. Phase objection and timeout.

PhasingObjection

UVM Coverage Collector & Reporting

Integrating covergroups in a UVM subscriber, analysis port subscription, $get_coverage / $set_coverage_db_name, coverage report in check_phase, merging coverage databases.

CoverageReporting

Track 4

Coverage & Formal — Days 16–20

Constrained Random Verification

rand/randc, constraint blocks, weighted distribution (dist), solve…before, implication constraints (→), disable randomize, randomize() with {}, constraint inheritance.

Coverage-Driven Verification & Closure

Coverage-driven workflow: cross coverage goals, grading methodology, directed tests for holes, regression strategy, merge+report flow (Synopsys VCS, Cadence Xcelium, QuestaSim).

Code Coverage — Line, Toggle, FSM

Line/statement, branch, toggle, expression, FSM coverage — what each type measures, exclusion syntax, why 100% code coverage is not enough, combining with functional coverage.

Formal Verification Basics

Model checking vs simulation, property checking in JasperGold/VC Formal, assume/assert/cover, bounded model check (BMC), unbounded proof, cone of influence, CEX debug.

FormalModel Check

Equivalence Checking — LEC

Logical Equivalence Checking RTL vs gate-level, Synopsys Formality / Cadence Conformal flow, key points (flip-flops, black boxes), scan mapping, ECO re-verification.

Track 5

Protocol & Interview Prep — Days 21–25

AXI4 Verification Testbench

AXI4 protocol rules encoded as SVA, UVM VIP architecture for AXI4, VALID/READY handshake coverage, burst type coverage, error injection (SLVERR/DECERR), compliance checklist.

FIFO Verification — Corner Cases

Full/empty/overflow/underflow SVA, simultaneous read-write, pointer gray code checks, async FIFO CDC correctness, constrained random test for depth boundary stress.

FIFOCorner Cases

Clock Domain Crossing (CDC) Verification

SpyGlass CDC analysis, set_false_path vs set_max_delay -datapath_only, multi-bit CDC issues, handshake protocol checks, formal CDC proof setup, simulation coverage for sync chains.

Low Power (UPF) Verification

UPF power domains, supply sets, isolation cells, retention registers, level shifters — how to verify power-aware designs with Synopsys MVRC / Cadence CPF simulation.

Top 50 DV Interview Questions

50 most-asked verification engineering interview questions with model answers: UVM, SVA, coverage, formal, CDC, testbench architecture, SV OOP, race conditions, and debugging.