128 Bytes Internal Data RAM (00H–7FH) and SFR Memory Space (80H–FFH)
| Address | Hex Bytes | Disassembled Instruction | Cycles |
|---|---|---|---|
| Assemble code to inspect ROM memory. | |||
Real-time hardware counter visualization and vector interrupt routing
| Vector | Interrupt Source | Flag | Enable Bit (IE) | Priority (IP) | Status |
|---|---|---|---|---|---|
0000H |
Power-On Reset | PIN RST | Always Enabled | Highest | Ready |
0003H |
External Interrupt 0 (INT0) | IE0 (TCON.1) | EX0 (IE.0): 0 | PX0 (IP.0): 0 | Idle |
000BH |
Timer 0 Overflow (TF0) | TF0 (TCON.5) | ET0 (IE.1): 0 | PT0 (IP.1): 0 | Idle |
0013H |
External Interrupt 1 (INT1) | IE1 (TCON.3) | EX1 (IE.2): 0 | PX1 (IP.2): 0 | Idle |
001BH |
Timer 1 Overflow (TF1) | TF1 (TCON.7) | ET1 (IE.3): 0 | PT1 (IP.3): 0 | Idle |
0023H |
Serial UART (RI / TI) | RI/TI (SCON) | ES (IE.4): 0 | PS (IP.4): 0 | Idle |
Hands-on practical experiments covering embedded programming from basic GPIO to timers, interrupts, and UART communication.
An engineering walkthrough of the Intel 8051 architecture, covering the CPU datapath, internal RAM organization, Special Function Registers, the 6 addressing modes, and machine cycle calculations.
The 8051 CPU is built around an 8-bit Arithmetic Logic Unit (ALU) connected to the internal 8-bit system data bus. The ALU performs 8-bit additions, subtractions, multiplications, divisions, boolean bit manipulations, and logical operations. Operands are supplied via Accumulator A and Temporary Register 1.
MUL AB) and division (DIV AB). Otherwise functions as a general scratchpad register.The 128 bytes of internal data RAM (addresses 00H to 7FH) are divided into three physical functional partitions:
32 bytes divided into 4 banks (Bank 0, 1, 2, 3), each containing 8 working registers (R0–R7). Bank selection is controlled by bits RS1 (PSW.4) and RS0 (PSW.3).
16 bytes containing 128 individually addressable bit locations (bit addresses 00H through 7FH). Can be read, set, or cleared using boolean instructions like SETB 05H.
80 bytes of general-purpose data memory. The 8051 stack pointer (SP) operates in this internal RAM space, pre-incrementing on PUSH and post-decrementing on POP.
Complete reference manual for all 111 instructions of the classic Intel 8051 microprocessor family.
The 8051 is a Harvard-architecture 8-bit microcontroller featuring separate address and data spaces for Program Memory (ROM) and Data Memory (RAM). It has an 8-bit ALU, 128 bytes of internal RAM, 4KB on-chip ROM, four 8-bit parallel I/O ports, two 16-bit timers/counters, a full-duplex UART, and five interrupt sources.
The 8051 has 4 register banks (Bank 0, Bank 1, Bank 2, Bank 3) located in internal RAM from address 00H to 1FH. Each bank contains 8 working registers (R0 through R7). The active register bank is selected by bits RS1 (PSW.4) and RS0 (PSW.3).
Internal RAM addresses 20H to 2FH (16 bytes = 128 bits) are individually bit-addressable with bit addresses 00H to 7FH. In addition, Special Function Registers whose byte addresses end in 0 or 8 (such as ACC, B, PSW, P0–P3, TCON, SCON, IE, IP) are also bit-addressable.
Upon hardware reset, SP is loaded with 07H. Because the 8051 stack pre-increments before pushing data, the first PUSH instruction writes to address 08H (the start of Register Bank 1). To avoid corrupting Register Banks 1–3, programmers typically re-initialize SP to 30H or higher in their initialization routines.
1) Immediate Addressing (e.g. MOV A, #25H), 2) Register Addressing (e.g. MOV A, R3), 3) Direct Addressing (e.g. MOV A, 30H), 4) Register Indirect Addressing (e.g. MOV A, @R0), 5) Indexed Addressing (e.g. MOVC A, @A+DPTR), and 6) Bit Addressing (e.g. SETB P1.0).
In Mode 1, the timer operates as a full 16-bit counter using both TL and TH registers (counting from 0000H to FFFFH). In Mode 2 (8-bit Auto-Reload), TL counts from its initial value up to FFH; upon overflow, it automatically reloads the value stored in TH and sets the TF overflow flag, which is commonly used to generate baud rates for the UART.
Reset vectors to 0000H; External Interrupt 0 (INT0) vectors to 0003H; Timer 0 Overflow (TF0) vectors to 000BH; External Interrupt 1 (INT1) vectors to 0013H; Timer 1 Overflow (TF1) vectors to 001BH; Serial Communication (RI/TI) vectors to 0023H.
DA A adjusts the 8-bit result in Accumulator A after an ADD or ADDC operation to produce two packed BCD digits. If the lower 4 bits exceed 9 or AC is set, it adds 06H. If the upper 4 bits exceed 9 or CY is set, it adds 60H and sets CY.
SJMP (Short Jump) is a 2-byte instruction with a relative offset between -128 and +127 bytes. AJMP (Absolute Jump) is a 2-byte instruction allowing branching within the same 2KB memory page. LJMP (Long Jump) is a 3-byte instruction with a full 16-bit address allowing branching anywhere in 64KB ROM.
MUL AB multiplies the unsigned 8-bit integers in A and B. The lower 8 bits of the product are placed in A, and the upper 8 bits in B. CY is always cleared. The overflow flag (OV) is set to 1 if the product exceeds 255 (i.e., if register B is non-zero); otherwise OV is cleared.
DIV AB divides the unsigned integer in A by B. The integer quotient is placed in A and the remainder in B. CY is always cleared. If B is zero, OV is set to 1 to indicate division-by-zero error, and the contents of A and B remain undefined.
DPTR is a 16-bit register composed of two 8-bit registers: DPH (high byte at 83H) and DPL (low byte at 82H). It is primarily used to address 64KB external RAM (via MOVX) and look up tables in Program ROM (via MOVC A, @A+DPTR).
In Mode 1, the UART operates as a 10-bit full-duplex asynchronous serial port (1 start bit, 8 data bits, 1 stop bit). The baud rate is variable and determined by the overflow rate of Timer 1 operating in Mode 2 (8-bit auto-reload).
Yes! EcrioniX 8051 Studio runs 100% in your browser. It includes a two-pass assembler, cycle-accurate instruction executor, live register inspector, memory matrix, and a virtual hardware board with LEDs, 7-segment, LCD, and UART.
Yes. It adheres strictly to the classic Intel 8051 instruction set and addressing modes, compatible with textbook examples (Mazidi, Ayala, Calcutt) and standard university lab curricula.