What is the switching threshold VM of a CMOS inverter?

VM is the input voltage at which Vout = Vin. For a symmetric CMOS inverter (kn=kp), VM = VDD/2. It can be shifted by changing the W/L ratio of NMOS or PMOS.

How do noise margins NML and NMH relate to VIL and VIH?

NML = VIL − VOL and NMH = VOH − VIH. VIL and VIH are the input voltages where the VTC slope equals −1 (unity gain points). For ideal CMOS, VOL=0 and VOH=VDD.

Why does PMOS need to be wider than NMOS in a standard CMOS process?

Hole mobility (µp) is roughly half electron mobility (µn). To get equal drive strength and center VM at VDD/2, the PMOS width must be approximately 2× the NMOS width.

CMOS Inverter & VTC Interactive Lab

What is the Voltage Transfer Characteristic (VTC)?

The VTC plots DC output voltage (V_out) vs. DC input voltage (V_in) of a CMOS inverter. It reveals five operating regions, determines noise margins, and defines the switching threshold V_M — the input voltage at which V_out = V_in.

Five Operating Regions

Region	V_in range	NMOS state	PMOS state	V_out
1	0 → V_tn	OFF	Linear (deep)	≈ V_DD (HIGH)
2	V_tn → V_M	Saturation	Linear	High → falling
3	≈ V_M	Saturation	Saturation	Steep transition
4	V_M → V_DD+V_tp	Linear	Saturation	Low → falling
5	V_DD+V_tp → V_DD	Linear (deep)	OFF	≈ 0 (LOW)

Switching Threshold V_M

At V_M, both transistors are in saturation. Setting I_Dn = I_Dp and V_out = V_in = V_M:

VM = (VDD + Vtp + Vtn·√(kn/kp)) / (1 + √(kn/kp)) When kn = kp → VM = VDD/2 (symmetric inverter) When kn > kp → VM shifts below VDD/2 (NMOS stronger) When kp > kn → VM shifts above VDD/2 (PMOS stronger)

Noise Margins

V_IL: maximum input voltage still recognized as logic LOW — the point where |dV_out/dV_in| = 1 on the HIGH side of the VTC.

V_IH: minimum input voltage recognized as logic HIGH — where |dV_out/dV_in| = 1 on the LOW side.

NML = VIL − VOL (LOW noise margin, ideally = VIL since VOL ≈ 0) NMH = VOH − VIH (HIGH noise margin, ideally = VDD − VIH since VOH ≈ VDD) For symmetric CMOS: NML ≈ NMH ≈ 3VDD/8 (approximately)

Effect of W/L Ratio (k_n / k_p)

Increasing k_n (wider NMOS or stronger NMOS process) shifts V_M lower — the NMOS overpowers the PMOS earlier. In standard CMOS processes, µ_p ≈ µ_n/2, so PMOS is made 2× wider to equalize drive strength and center V_M at V_DD/2.

Effect of Channel Length Modulation (λ)

With λ > 0, drain current in saturation is I_D = (k/2)(V_GS−V_t)²(1+λV_DS). This slightly raises current in saturation, compressing the flat output regions. At Region 3, both transistors remain in saturation simultaneously — with λ, the slope is slightly less steep but V_M is nearly unchanged.

CMOS Inverter Advantages

Zero static power: In steady state, one transistor is always OFF → no DC path between V_DD and GND. Only dynamic power (C·V²·f) during switching. Full swing: V_OH = V_DD, V_OL = 0 (ideal). Symmetric noise margins: when properly sized. These properties made CMOS the dominant logic family from the 1980s onwards.

CMOS Inverter VTC Lab