OpenLane is an automated RTL-to-GDSII flow built by efabless on top of open-source EDA tools: Yosys (synthesis), OpenROAD (placement, CTS, routing), Magic (DRC, GDSII), and Netgen (LVS). It targets the SkyWater SKY130 130nm open-source PDK and lets anyone tape out a real chip for free or at very low cost through the Google-sponsored MPW shuttle program.

How do I install OpenLane 2?

OpenLane 2 is distributed as a Python package. Install with: pip install openlane. You also need Nix package manager for managing the EDA tool dependencies, or you can use the Docker-based approach with the openlane Docker image. The fastest start is: pip install openlane && openlane --dockerized --run-example spm.

What is the difference between OpenLane 1 and OpenLane 2?

OpenLane 1 uses a Tcl-based flow with config.tcl or config.json. OpenLane 2 (openlane2) is a complete rewrite in Python with a typed, composable API, better reproducibility via Nix, and config.json only. OpenLane 2 is the current actively developed version and recommended for new designs.

OpenLane Guide — RTL to GDSII Open-Source Flow

Q: What PDK does OpenLane use?

OpenLane primarily targets the SkyWater SKY130 130nm PDK, which is the first fully open-source process design kit. It also supports GF180MCU (GlobalFoundries 180nm). The PDK provides standard cell libraries, SPICE models, DRC rules, and LVS rule files needed to physically implement a design.

Q: What is the Google MPW shuttle program?

Google's Multi-Project Wafer (MPW) shuttle program sponsors free silicon fabrication runs using the SKY130 PDK. Multiple open-source designs are combined on a single wafer, splitting the cost. Successful submissions are fabricated into real chips and sent back to designers — entirely free. OpenLane is the standard flow used for MPW submissions.

▶ Installation

OpenLane 2 (Recommended)

Python-based rewrite with Nix for reproducible tool management. Best for new designs. Requires Python 3.8+ and Nix.

OpenLane 1 (Legacy)

Tcl/Makefile-based flow, Docker image bundles all tools. Widely used in existing tutorials and the MPW shuttle.

System Requirements

Linux (Ubuntu 20.04+ recommended) or macOS. Docker Desktop for OL1. 8 GB RAM minimum; 16 GB for complex designs. ~20 GB disk space.

bash — OpenLane 2 (pip + Nix)

# 1. Install Nix (required for tool management)
sh <(curl -L https://nixos.org/nix/install) --daemon

# 2. Install OpenLane 2
pip install openlane

# 3. Run the built-in SPM example to verify
openlane --dockerized --run-example spm

# 4. Or run your own design
openlane --dockerized config.json

bash — OpenLane 1 (Docker)

# 1. Clone and set up
git clone https://github.com/The-OpenROAD-Project/OpenLane.git
cd OpenLane
make setup          # pulls Docker image + PDK

# 2. Start interactive Docker shell
make mount

# 3. Run the default spm example inside Docker
./flow.tcl -design spm

# 4. Run your own design
./flow.tcl -design your_design -tag run1

▶ Quick Start — Minimal config.json

Create a directory for your design with the Verilog file and a config.json:

verilog — my_design/src/counter.v

module counter (
  input  wire       clk,
  input  wire       rst,
  output reg  [7:0] count
);
  always @(posedge clk or posedge rst)
    if (rst) count <= 8'b0;
    else     count <= count + 1;
endmodule

json — my_design/config.json

{
  "DESIGN_NAME": "counter",
  "VERILOG_FILES": ["src/counter.v"],
  "CLOCK_PORT": "clk",
  "CLOCK_PERIOD": 10,
  "pdk": "sky130A",
  "STD_CELL_LIBRARY": "sky130_fd_sc_hd"
}

bash — run the flow

# OpenLane 2
cd my_design
openlane --dockerized config.json

# OpenLane 1 (inside Docker mount)
./flow.tcl -design my_design

▶ Flow Stages — What Happens Inside

1 Synthesis Yosys + ABC ▶

Translates RTL Verilog into a gate-level netlist using cells from the SKY130 standard cell library. Yosys performs RTL elaboration, optimization, and technology mapping. ABC handles logic optimization and cell selection.

Inputs: Verilog RTL, Liberty timing files (.lib)
Outputs: Gate-level netlist (.v), synthesis report, area report
Key config: SYNTH_STRATEGY, SYNTH_MAX_FANOUT, MAX_FANOUT_CONSTRAINT
Common issue: Latch inferred instead of FF → use synchronous reset or add always @(posedge clk)

2 Floorplanning OpenROAD ▶

Defines the chip die area, places I/O pads, inserts power/ground rings and stripes, and creates the power delivery network (PDN). The core utilization ratio controls how much area is used for cells vs routing.

Inputs: Gate-level netlist, die/core size constraints
Outputs: DEF file with die area, I/O placement, PDN
Key config: FP_CORE_UTIL (default 50%), DIE_AREA, FP_IO_MODE
Tip: Start with FP_CORE_UTIL = 40–50% to leave routing headroom

3 Placement OpenROAD RePlAce ▶

Places standard cells inside the core area to minimize wire length and meet timing. Done in two passes: global placement finds approximate positions; detailed placement legalises them onto the grid.

Inputs: Floorplanned DEF, gate-level netlist
Outputs: Legally placed DEF, placement report
Key config: PL_TARGET_DENSITY, PL_RANDOM_GLB_PLACEMENT
Common issue: Overlap errors → reduce PL_TARGET_DENSITY or increase die area

4 Clock Tree Synthesis (CTS) TritonCTS ▶

Builds a balanced clock distribution network that delivers the clock signal to all flip-flops with minimal skew. Inserts clock buffers/inverters in a tree topology. Clock skew directly affects hold timing.

Inputs: Placed DEF, clock constraints (period, port)
Outputs: DEF with clock tree, CTS report (skew, latency)
Key config: CTS_TARGET_SKEW, CTS_CLK_BUFFER_LIST
Tip: After CTS, always check hold slack — it often becomes positive before this step but may go negative after

5 Routing TritonRoute ▶

Connects all placed cells with metal wires according to the netlist. Global routing assigns wire segments to routing regions; detailed routing assigns exact tracks. Uses the SKY130 metal stack (li1, met1–met5).

Inputs: CTS DEF, routing constraints
Outputs: Fully routed DEF, routing report, DRC violations count
Key config: ROUTING_CORES, GLB_RT_MAX_DIODE_INS_ITERS
Common issue: Unrouted nets → increase die size or reduce utilization

6 DRC & LVS Sign-off Magic + Netgen ▶

DRC (Design Rule Check) — Magic verifies that the layout meets all physical manufacturing rules: minimum width, spacing, enclosure, via rules for the SKY130 PDK. Zero DRC violations required for tape-out.

LVS (Layout vs Schematic) — Netgen compares the extracted netlist from the layout against the gate-level netlist to ensure they match electrically. Any mismatch means a routing bug.

Key config: MAGIC_DRC_USE_GDS, LVS_INSERT_POWER_PINS
Common fix: Antenna violations → set DIODE_INSERTION_STRATEGY = 3

7 GDSII Generation Magic / KLayout ▶

Writes the final GDSII (Graphic Design System II) file — the industry-standard format for chip layout data sent to a fab. This file encodes all polygons for every metal/poly/diffusion layer on the chip.

Output file: runs/<tag>/results/final/gds/design.gds
View in: KLayout (free) — open .gds and navigate layers
Tape-out: Submit .gds + .lef + .spice to MPW shuttle via efabless Caravel harness

▶ config.json Key Parameters

json — config.json full example

{
  // Design
  "DESIGN_NAME": "my_chip",
  "VERILOG_FILES": ["src/*.v"],
  "CLOCK_PORT": "clk",
  "CLOCK_PERIOD": 10,          // 10 ns = 100 MHz

  // PDK
  "pdk": "sky130A",
  "STD_CELL_LIBRARY": "sky130_fd_sc_hd",

  // Floorplan
  "FP_CORE_UTIL": 45,           // 45% utilisation
  "DIE_AREA": "0 0 200 200",  // microns
  "FP_IO_MODE": 1,             // 0=matched, 1=random equidistant

  // Placement
  "PL_TARGET_DENSITY": 0.55,

  // Routing
  "ROUTING_CORES": 4,
  "DIODE_INSERTION_STRATEGY": 3, // antenna fix

  // Sign-off
  "MAGIC_DRC_USE_GDS": true,
  "RUN_LVS": true
}

Parameter	Default	Description
CLOCK_PERIOD	10	Target clock period in nanoseconds. Sets timing constraints for synthesis and STA.
FP_CORE_UTIL	50	Core utilization percentage. Lower values leave more room for routing; start at 40–50%.
PL_TARGET_DENSITY	0.55	Cell density target for global placement (0–1). Higher = denser, may cause routing congestion.
SYNTH_STRATEGY	AREA 0	Synthesis optimization goal: AREA 0–3, DELAY 0–4. DELAY optimizes for timing; AREA for size.
MAX_FANOUT_CONSTRAINT	10	Maximum fanout per cell output before buffering. Reduce to 5 for high-speed designs.
DIODE_INSERTION_STRATEGY	3	Antenna rule violation fix strategy. 3 = insert diodes during global routing (recommended).
GLB_RT_ADJUSTMENT	0	Reduce routing capacity by this fraction (0–1) to leave margin. Try 0.1 if congested.
MAGIC_DRC_USE_GDS	true	Run Magic DRC on the final GDS (more accurate than DEF-based DRC).

▶ Key Output Files

All outputs land in runs/<tag>/results/ and runs/<tag>/reports/:

.gds / .gds2

Final chip layout in GDSII format. Open in KLayout. Submit this to MPW shuttle / foundry.

.lef

Library Exchange Format — abstract view of the cell with port locations and metal layers. Used by place-and-route tools.

.spice / .lvs.spice

SPICE netlist extracted from the final layout. Netgen uses this for LVS comparison against the gate-level netlist.

synthesis/1-synthesis.v

Gate-level netlist after Yosys synthesis. Contains only standard cells from the SKY130 library.

synthesis/reports/area.rpt

Cell count, number of wires, flip-flop count, and estimated chip area after synthesis.

signoff/drc.rpt

Magic DRC report. Must show 0 violations for tape-out. Lists violation type, layer, and coordinates.

signoff/lvs.rpt

Netgen LVS report. "Circuits match" = layout is electrically correct. Any mismatch is a critical bug.

sta/min_max_ss_100C.rpt

OpenSTA timing report at slow-slow corner, 100°C. Contains setup/hold slack for all paths.

▶ Common Issues & Tips

DRC Antenna Violations

Long metal wires accumulate charge during fab that can destroy gate oxide. Fix: set DIODE_INSERTION_STRATEGY: 3. This auto-inserts antenna diodes during routing.

Routing Congestion

Too many wires squeezed into a small area. Fix: lower FP_CORE_UTIL to 35–40%, or increase DIE_AREA. Also try GLB_RT_ADJUSTMENT: 0.1.

Timing Violations

Negative setup slack after routing. Fix: try SYNTH_STRATEGY: "DELAY 1", increase CLOCK_PERIOD, or pipeline your design.

LVS Mismatch

Layout netlist doesn't match schematic. Most often from a missing or shorted power net. Check that VDD/VSS are properly connected in the PDN and all cells have power pins.

Frequently Asked Questions

What is OpenLane?

OpenLane is an automated RTL-to-GDSII flow maintained by efabless and built on open-source tools: Yosys for synthesis, OpenROAD for placement and routing, Magic for layout and DRC, and Netgen for LVS. It targets the SkyWater SKY130 130nm open-source PDK and makes it possible for anyone to design and tape out a real integrated circuit.

What PDK does OpenLane use?

OpenLane primarily uses SkyWater SKY130 — a fully open-source 130nm PDK developed with Google. It provides standard cell libraries (sky130_fd_sc_hd, sky130_fd_sc_hs, etc.), SPICE models, DRC/LVS rules, and GDSII frames. OpenLane 2 also supports GF180MCU (GlobalFoundries 180nm). The SKY130 PDK was the first open-source PDK and enabled the Google/efabless MPW shuttle program.

How do I view the final GDSII layout?

Use KLayout (free, open-source). Open KLayout, go to File → Open, and load the .gds file from runs/<tag>/results/final/gds/. Use Ctrl+scroll to zoom. Layer colours correspond to different metal/poly/diffusion layers in the SKY130 layer stack (li1, met1–met5, poly, ndiff, pdiff, nwell, etc.).

What is the Google MPW shuttle program?

Google's Multi-Project Wafer (MPW) shuttle sponsors free fabrication runs on SKY130. Multiple open-source designs are combined on one wafer, splitting costs to near zero. Accepted designs are fabricated and chips are shipped to designers. OpenLane with a Caravel harness wrapper is the standard submission method. Shuttles run periodically through the efabless.com platform.

What is the Caravel harness?

Caravel is a pre-designed SoC harness provided by efabless for MPW submissions. It includes a RISC-V (PicoRV32) processor, GPIO pads, power management, and a user project area — a 2.9 mm × 3.5 mm space where you plug in your design. Your Verilog module connects via the user_project_wrapper interface. Using Caravel means the chip I/O, power, and clock are already handled for you.

How long does a full OpenLane run take?

A small design (few hundred cells, like an 8-bit counter) typically completes in 5–15 minutes on a modern laptop with 4 cores. A medium design (few thousand cells) takes 30–90 minutes. Very large designs (100k+ cells) can take several hours. The routing step is usually the bottleneck. Running with ROUTING_CORES: 4 or more speeds things up significantly.

What is OpenLane 2 vs OpenLane 1?

OpenLane 1 uses a Tcl/Makefile flow and a Docker image with all tools pre-bundled. It's mature and well-documented for MPW submissions. OpenLane 2 is a complete Python rewrite with a composable, typed API, Nix for reproducible tool management, and better introspection. OL2 is the actively developed version — use it for new designs. Both use the same underlying EDA tools (Yosys, OpenROAD, Magic, Netgen).

OpenLane — Full-Chip Physical Design from RTL to GDSII