Serial Protocol Lab

SPI (Serial Peripheral Interface) is a synchronous, full-duplex serial communication protocol developed by Motorola in the mid-1980s. It uses four wires: SCLK (clock), MOSI (Master Out Slave In), MISO (Master In Slave Out), and CS/SS (Chip Select, active LOW). Unlike I²C, SPI has no addressing mechanism — the master selects a specific slave by asserting its CS pin LOW. Multiple slaves share the same SCLK/MOSI/MISO bus (daisy-chain or parallel CS lines).

SPI is a shift register protocol: internally, master and slave each have an N-bit shift register. On every clock edge, one bit exits the master's register via MOSI and enters the slave, while one bit exits the slave via MISO and enters the master. After N clocks, a complete N-bit word has been exchanged — simultaneously in both directions. There is no ACK; the master must know the protocol of each device to interpret responses.

• SCLK — Serial clock, always driven by master. Can be MHz to hundreds of MHz.
• MOSI — Master Out Slave In. Data from master to slave, shifted MSB-first by convention.
• MISO — Master In Slave Out. Data from slave to master, tri-stated when CS is HIGH.
• CS / SS — Chip Select (active LOW). One per slave. Master asserts LOW to begin, deasserts HIGH to end.

CPOL (Clock Polarity) sets the idle state of SCLK: 0 = idle LOW, 1 = idle HIGH.
CPHA (Clock Phase) sets which edge is the capture edge: 0 = leading edge, 1 = trailing edge.
Leading edge is the first active transition after CS asserts (rising for CPOL=0, falling for CPOL=1).

• CS must assert before SCLK starts. Some devices require t_CS_setup > 5 ns.
• MOSI is valid before the capture edge. t_setup must be met.
• MISO is released when CS deasserts. The slave tri-states MISO to allow bus sharing.
• MSB-first is conventional but some devices (e.g. certain ADCs) use LSB-first. Always check the datasheet.
• Word size varies: 8-bit is most common, but 16- and 32-bit transfers exist.
• No ACK. The master must implement protocol-level validation (e.g. read a status register after write).

UART (Universal Asynchronous Receiver-Transmitter) is a hardware communication protocol that uses asynchronous serial communication with configurable speed. Unlike I²C and SPI, UART has no clock line — both sender and receiver independently generate their own bit-rate clocks that must be pre-configured to the same baud rate (bits per second). The idle line state is logic HIGH (mark). Transmission begins with a mandatory START bit (logic LOW), which lets the receiver detect the start of a frame and synchronise its sampling clock.

Data bits are transmitted LSB first by convention (bit 0 before bit 7). An optional parity bit follows the data for error detection. One or two STOP bits (logic HIGH) end the frame, giving the receiver time to process before the next frame. Because there is no clock recovery mechanism, baud rates must match within ±2–3% — any mismatch causes the sampling point to drift across the frame.

Example: 8N1 (8 data bits, No parity, 1 stop bit) transmitting 0x41 ('A' = 0b01000001)

Note: 0x41 = 0b01000001. LSB (bit 0 = 1) is sent first → D0=1, then D1..D6=0, D7=0.

• Baud rate: Bits per second. At 115200 baud, each bit = 1/115200 ≈ 8.68 µs.
• LSB first: Bit 0 (LSB) is always transmitted first; receiver reverses the order.
• START bit edge: The falling edge of the START bit is the sync event — receiver's sampling clock starts from this edge + 0.5 bit periods (samples at mid-bit for maximum noise margin).
• Parity — Even: Parity bit is chosen so the total number of 1s (data + parity) is even.
• Parity — Odd: Total number of 1s is odd. Neither detects 2-bit errors.
• Stop bit(s): Line returns to HIGH. The receiver checks this; a LOW stop bit is a framing error.
• Oversampling: UARTs typically sample each bit at 8× or 16× the baud rate and take a majority vote for noise rejection.
• RS-232 vs TTL: RS-232 uses ±12 V logic (HIGH = -12 V, LOW = +12 V — inverted!). TTL UART uses 3.3 V or 5 V logic. Always match levels with a level-shifter or MAX232.
• Flow control — RTS/CTS: Hardware flow control where receiver asserts CTS LOW to allow transmission. Prevents buffer overrun on slow receivers.

Debug console (printf over USB-UART), GPS receivers (NMEA sentences), Bluetooth UART (HC-05, HM-10), GSM/LTE modems (AT commands), bootloader flashing, data logging. UART is the universal "wire" for quick embedded communication.