Define your control & status registers with named bit-fields — width, offset, access, reset — and export from one source of truth: synthesizable Verilog (APB3 / AXI4-Lite + bridge), a UVM RAL model, IP-XACT XML, and a register datasheet PDF.
This tool builds a standard APB3 slave wrapper around your register file. Each register sits at an address offset and contains one or more named bit-fields. Fields auto-pack from the LSB upward — the Bits column shows the computed [msb:lsb] range. Each field becomes its own storage element and hardware port, assembled into the register word inside a synchronous write block and a combinational read multiplexer. PREADY is tied high (zero wait states) and PSLVERR is tied low.
For example, a CTRL register with fields ENABLE[0], MODE[2:1] and START[3] generates ctrl_enable_q, ctrl_mode_q and a ctrl_start_o pulse — each driven from / read into the correct slice of PWDATA/PRDATA.
Select AXI4-Lite as the bus interface to wrap the register block with an AXI4-Lite → APB bridge — see that page for the bridge architecture, FSM and timing.
_o to hardware._i; software reads it._o; reads return 0._set_i; software clears by writing 1.An APB transfer has a setup phase (PSEL=1, PENABLE=0) and an access phase (PSEL=1, PENABLE=1). A write commits when PSEL & PENABLE & PWRITE is high. A read drives PRDATA from the address-decoded mux. The generated module follows this exactly.
A set of memory-mapped control/status registers (CSRs) the CPU accesses over the APB3 bus using PSEL, PENABLE, PWRITE, PADDR, PWDATA and PRDATA to configure and monitor a hardware block.
Yes — a synchronous write block, combinational read mux, PREADY high and PSLVERR low. Only synthesizable constructs, compatible with Vivado, Quartus, Yosys and Synopsys DC.
Wire the APB ports to your master/bridge. RW/WO registers give an output (_o), RO registers take an input (_i), W1C registers take a set input (_set_i) and give a status output (_o).
Yes. Switch the output tab to UVM RAL to get a SystemVerilog package with a uvm_reg class per register (fields configured with size, lsb, access, reset) and a uvm_reg_block that maps each register at its offset in a default_map. Download it as <module>_ral_pkg.sv and drop it into your UVM testbench.
Yes. The IP-XACT tab emits an IEEE 1685-2014 component with a memoryMap / addressBlock, one register per register and a field per bit-field (bitOffset, bitWidth, access, reset; W1C uses modifiedWriteValue=oneToClear). Import it into Vivado IP Integrator, Magillem, or any IP-XACT-aware flow.