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SKY130 Floorplan Tool

Paste your Verilog RTL — synthesize with Yosys and run OpenROAD floorplan on the SkyWater SKY130 PDK. Get die area, core area, utilisation and row count in seconds.

Yosys Synthesis OpenROAD Floorplan SkyWater SKY130 HD 40% Core Utilisation Free · No Install
Verilog RTL
Ctrl+Enter to run
Floorplan Results
Load an example or paste Verilog,
then click Run SKY130 Floorplan
How It Works

Three backend steps run on each request — all open-source tools, no proprietary EDA licenses required.

Step 1
Yosys Synthesis
Your Verilog is synthesized against the SKY130 HD liberty file (.lib). Yosys maps the design to standard cells and reports gate count and chip area.
Step 2
Die Size Calculation
The die dimensions are computed from the synthesized area using a 40% core utilisation target — a standard conservative starting point.
Step 3
OpenROAD Floorplan
OpenROAD reads the SKY130 tech LEF and merged cell LEF, then calls initialize_floorplan and report_design_area to return the physical dimensions.
Result
Area Metrics
Die area, core area, cell area (µm²), actual utilisation %, and row/site count are returned and displayed in a structured card.
Example: 4-bit Counter

A synchronous 4-bit counter with active-high reset. A typical small design to test the flow — synthesises to ~12 standard cells.

Verilog 
module counter(
  input  wire       clk, rst,
  output reg  [3:0] count
);
  always @(posedge clk or posedge rst)
    if (rst) count <= 4'd0;
    else     count <= count + 1;
endmodule
FAQ
What is a floorplan in VLSI?+
Floorplan is the first physical design step after synthesis. It defines the die boundary, places rows of standard cells, and estimates the chip area needed for a given netlist at a target utilisation.
What is the SKY130 PDK?+
SKY130 is SkyWater Technology's open-source 130nm CMOS process design kit, released in 2020. It is used in Google's free MPW shuttle programs, making it the most accessible PDK for open chip design.
What does 40% utilisation mean?+
Core utilisation is the fraction of the core area occupied by standard cell logic. 40% is a conservative target that leaves room for routing, clock tree buffers, and decoupling capacitors. Higher utilisation means smaller die but more difficult routing.
What is OpenROAD?+
OpenROAD is an open-source RTL-to-GDSII physical design tool developed by UC San Diego and industry partners. It covers floorplanning, placement, clock tree synthesis, global and detailed routing. It is the core engine in the OpenLane automated flow.
Can I use this for real chip design?+
This tool provides accurate initial floorplan metrics using the real SKY130 PDK and OpenROAD. For a complete tape-out flow (placement, CTS, routing, DRC, GDSII), use the full OpenLane flow locally or via the efabless platform.