Lane marking detection, obstacle boundary extraction, traffic sign localization. A Sobel IP runs ahead of the CNN to reduce NPU workload by pre-highlighting edges at 60 fps.
High-speed optical scanners use Sobel IPs in FPGAs to detect defect edges on wafer surfaces in real time — far too fast for CPU-based processing at 4K resolution.
MRI, CT, and X-ray preprocessing pipelines embed Sobel filters to highlight tissue boundaries and organ contours before the radiologist or AI classifier sees the image.
Edge detection dramatically simplifies locating code regions in a frame. Embedded scanners (POS terminals, handheld readers) run Sobel in dedicated silicon to enable sub-millisecond decode.
Background-subtracted frames are edge-detected in FPGA to isolate moving object contours without streaming full pixel data to CPU — reduces bandwidth and wakes the system only on real events.
Industrial cameras feeding Xilinx/Intel FPGAs use Sobel IP cores as the first stage of an image-processing pipeline — before histogram equalization, optical flow, or CNN feature extraction.
Each incoming pixel is written into a circular SRAM or shift-register chain of depth frame_width. Three such buffers hold rows n−2, n−1, and n simultaneously. A new output pixel can be produced every clock once 2 full rows are buffered. This is the latency "fill" cost = 2×frame_width cycles at startup.
A 3×3 array of 8-bit registers (p00–p22) is fed from the three row-buffer tails and two additional per-row shift registers. On every clock, the window slides one pixel right — the leftmost column is discarded and a new rightmost column is clocked in from the three buffers. Registered output ensures clean timing to stage 3.
Both Gx and Gy are computed in the same clock cycle using only addition, subtraction, and 1-bit left shifts. The signed 10-bit results are registered at the end of this stage. No multipliers. Critical path = 3 additions + 1 left shift ≈ very short; this stage is never the timing bottleneck.
Absolute values of Gx and Gy are summed. The result is a 11-bit value (max = 4×255 = 1020). It is clamped to 255 before outputting as edge_out[7:0]. valid_out is asserted simultaneously.
| Port | Width | Dir | Description |
|---|---|---|---|
| clk | 1 | IN | System clock, rising-edge active |
| rst_n | 1 | IN | Active-low synchronous reset — clears all line buffers and pipeline regs |
| frame_width | 11 | IN | Horizontal pixel count of the frame (max 2048). Must be stable during a frame |
| valid_in | 1 | IN | Assert high when pixel_in holds a valid pixel. No gaps allowed mid-row |
| pixel_in | 8 | IN | Grayscale pixel value, 8-bit unsigned (0 = black, 255 = white) |
| valid_out | 1 | OUT | High when edge_out is valid. Delayed by 2 rows + 4 pipeline stages after first valid_in |
| edge_out | 8 | OUT | Edge magnitude = |Gx|+|Gy|, clamped to 8-bit. Bright = strong edge, 0 = flat region |
module sobel_core #( parameter IMG_W = 640 // max frame width (sets line-buffer depth) ) ( input wire clk, input wire rst_n, // input stream input wire valid_in, input wire [7:0] pixel_in, // 8-bit grayscale input wire [10:0] frame_width,// actual columns this frame // output stream output reg valid_out, output reg [7:0] edge_out // |Gx|+|Gy| clamped to 8-bit ); // ─── Stage 1: Line buffers ────────────────────────────────────── // Three circular FIFOs of depth IMG_W hold rows n-2, n-1, n // ─── Stage 2: 3×3 sliding window register ────────────────────── // reg [7:0] p[0:2][0:2]; (row, col) // ─── Stage 3: Gx / Gy (combinational, registered at output) ──── // Gx = (p[0][2]+2*p[1][2]+p[2][2]) - (p[0][0]+2*p[1][0]+p[2][0]) // Gy = (p[2][0]+2*p[2][1]+p[2][2]) - (p[0][0]+2*p[0][1]+p[0][2]) // ─── Stage 4: magnitude + clip ───────────────────────────────── // mag = |Gx| + |Gy|; edge_out = (mag > 255) ? 255 : mag[7:0] endmodule
Theory, block diagrams, port spec, pipeline timing — this page
sobel_core.v — line buffers, 3×3 window, Gx/Gy, magnitude
sobel_tb.v — reads grayscale hex, drives DUT, writes edge hex
gray → hex → iverilog → edge → PNG reconstruction
Upload any image → run Sobel DUT → download edge image
Yosys → SKY130 — gate count, area, critical path depth