Online STA Analyzer
Paste your Verilog design, set the clock frequency, and run OpenSTA static timing analysis on NanGate45 standard cells — directly in the browser. Instantly see setup slack, WNS, TNS, and critical path.
STA Theory — Concepts & How to Fix Violations
What is Slack?
Slack is the timing margin of a path — how much time is left over after accounting for all delays.
It is calculated as:
Slack = Required Arrival Time − Actual Arrival Time
Required time = clock period − setup_time_of_FF
Actual time = clock-to-Q delay + combinational path delay
Positive Slack (MET)
Data arrives with time to spare. Design runs at this frequency safely. You can push the clock faster until slack reaches 0.
Negative Slack (VIOLATED)
Data arrives too late — the flip-flop may capture wrong data. You must reduce frequency, add pipeline stages, or optimise the logic.
What are Timing Constraints?
Constraints tell the timing engine the clock frequency, I/O timing budget, and exceptions (false paths, multicycle paths).
They are written in Tcl / SDC format.
# Define a 10ns clock (100 MHz) on port "clk"
create_clock -period 10.0 [get_ports clk]
# Allow 1ns for external logic driving inputs
set_input_delay 1.0 -clock clk [get_ports rst]
set_input_delay 1.0 -clock clk [get_ports data_in]
# Allow 1ns for output load/routing
set_output_delay 1.0 -clock clk [all_outputs]
# Mark a path as not timing-critical (false path)
set_false_path -from [get_ports scan_en]
# Path that takes 2 clock cycles (multicycle)
set_multicycle_path 2 -setup -from [get_cells slow_div]
You can edit these constraints in the Applied Constraints panel that appears after a run, then click Re-run.
How to Fix Timing Violations (Reduce Negative Slack)
Lower Clock Frequency
Easiest fix — reduce frequency until slack ≥ 0. Try slider above. Trade-off: reduced performance.
Add Pipeline Registers
Split a long combinational path into two shorter stages by inserting a flip-flop in the middle. Doubles latency but allows 2× frequency.
Restructure Logic
Reduce logic depth — replace ripple-carry with carry-lookahead, reorder operations, remove glue logic on the critical path.
Use Faster Cells
Synthesis can use high-drive-strength cells on the critical path (faster but larger/higher power). Controlled via SDC set_sizing_opt or Yosys settings.
Frequently Asked Questions
What is Static Timing Analysis (STA)?
STA verifies that all timing paths in a digital design meet setup and hold constraints without running simulation. It computes worst-case propagation delay through every register-to-register path and checks whether data arrives before the clock edge captures it (setup check) and stays stable long enough after the clock edge (hold check).
What standard cell library is used?
This tool uses the NanGate45 Open Cell Library — a fictional 45nm standard cell library widely used in academic research and VLSI courses. Yosys maps your RTL to NanGate45 gates (AND2_X1, DFF_X1, INV_X1, etc.) and then OpenSTA computes timing using the Liberty timing models.
Why does timing fail at high frequencies?
Each gate adds propagation delay. At high clock frequencies, the clock period is very short, leaving little time for data to travel through combinational logic from one flip-flop to the next. When the total path delay exceeds the clock period minus setup time, you get a setup violation (negative slack).
How is clock period calculated from frequency?
Period (ns) = 1000 ÷ Frequency (MHz). Example: 100 MHz → 10 ns period. 500 MHz → 2 ns period. Input and output delays are set to 10% of the period automatically.
What does it mean if no clock is detected?
The tool looks for common clock port names (clk, clock, CLK). If your design is purely combinational or uses a different clock name, it runs an unconstrained analysis — reporting the longest combinational path without a frequency constraint.