5 hands-on examples using real Verilator + iverilog checks. Load a broken module, spot the issue, fix it, and run lint to confirm it's clean.
design.v — broken
IMPLICIT · Undeclared Net
A signal is used without being declared. In default Verilog this silently creates a 1-bit wire — dangerous if it's a typo.
Fix: declare the missing wire before using it.
Lint Output— not run
Run lint to see results.
How It Works
STEP 01
Pick an Example
Each example loads a broken Verilog module that contains one specific lint violation.
STEP 02
Read the Hint
The violation name, description, and fix hint are shown above the output pane.
STEP 03
Fix the RTL
Edit the code directly in the editor. The fix is usually one or two lines.
STEP 04
Run Lint
Click Run Lint. Verilator + iverilog check your code. Fix until the output shows Clean.
FAQ
What is Verilog linting?
Linting is static analysis of RTL code that catches bugs before simulation. It finds issues like undeclared wires, width mismatches, and undriven outputs that simulators may silently ignore.
What does Verilator --lint-only do?
It runs structural checks on Verilog/SystemVerilog without generating any simulation model. It is very fast and catches a wide range of RTL coding issues including WIDTH, UNDRIVEN, UNUSEDSIGNAL, and BLKSEQ.
Why is an implicit wire dangerous?
In standard Verilog, using an undeclared name auto-creates a 1-bit wire. A typo silently creates a new unconnected net instead of a compile error. Adding `default_nettype none turns this into a hard error.
Why use <= in clocked always blocks?
Non-blocking assignments (<=) correctly model flip-flop behavior — all right-hand sides are evaluated before any are written. Blocking (=) assignments in clocked blocks cause race conditions in simulation and synthesis mismatches.
What does a WIDTH warning mean?
A WIDTH warning means you are assigning or comparing signals of different bit widths. This can silently truncate or zero-extend values. Fix by matching widths explicitly using zero-extension or proper sizing of literals.
About the Verilog Linter — Catch RTL Bugs Early
Linting is the practice of statically analysing your RTL before simulation or synthesis to catch the classes of mistakes that are easy to make and expensive to find later. A linter reads your Verilog or SystemVerilog and flags suspicious constructs — the kind of issues that compile cleanly but cause subtle hardware bugs or wildly different behaviour between simulation and silicon.
Many of the hardest debugging sessions in digital design trace back to problems a linter would have caught instantly: an incomplete sensitivity list, a latch inferred where you wanted a flip-flop, a signal driven from two places, or a width mismatch that silently truncates a value. Running a lint pass turns hours of waveform hunting into a one-line warning.
Common issues linting catches
Inferred latches from incomplete if/case branches in combinational logic.
Sensitivity-list problems in classic always blocks.
Width mismatches and unintended truncation or sign extension.
Multiple drivers on the same net, and undriven/floating signals.
Blocking vs non-blocking misuse that causes simulation–synthesis mismatch.
Treat lint warnings as part of writing clean RTL, not an afterthought — fixing them early keeps a design robust as it scales. Pair this tool with our online Verilog simulator to write, lint and simulate your designs entirely in the browser.