UVM (Universal Verification Methodology) is a standardized SystemVerilog library (IEEE 1800.2) for building reusable, structured verification environments. It provides a set of base classes (uvm_test, uvm_env, uvm_agent, uvm_driver, uvm_monitor, uvm_scoreboard), a phasing mechanism that sequences test execution, a factory for object creation and override, a configuration database for passing settings, and a reporting system. UVM replaced earlier methodologies (VMM, OVM) and is now the industry standard for chip verification.

What is the difference between uvm_component and uvm_object?

uvm_component is the base class for structural, persistent testbench components — agents, drivers, monitors, scoreboards. Components have a fixed position in the testbench hierarchy (a path like 'uvm_test_top.env.agent.driver'), participate in phasing (build_phase, connect_phase, run_phase, etc.), and exist for the lifetime of the simulation. uvm_object is the base class for transient data objects — sequence items, sequences, configuration objects. Objects have no fixed hierarchy position and no phases. They are created and destroyed dynamically during the test.

UVM phases are a synchronized execution framework that ensures all components complete one stage before the next begins. The main phases in order are: build_phase (construct child components), connect_phase (wire TLM ports), start_of_simulation_phase, run_phase (time-consuming, where stimulus runs), extract_phase, check_phase, report_phase, and final_phase. The run_phase uses objections — a test calls raise_objection to prevent simulation from ending, runs stimulus, then calls drop_objection to allow the simulation to end gracefully.

How do you run a UVM test from the command line?

UVM tests are selected at runtime using the +UVM_TESTNAME plusarg: +UVM_TESTNAME=my_test_class. The UVM factory looks up the class by name and creates it. You can also control verbosity with +UVM_VERBOSITY=UVM_HIGH (or UVM_LOW, UVM_MEDIUM, UVM_DEBUG). The top-level module calls run_test() which hands control to the UVM infrastructure. Example: vsim -do 'run -all' +UVM_TESTNAME=base_test +UVM_VERBOSITY=UVM_HIGH tb_top

Introduction to UVM — Day 6 | EcrioniX Verification Series

Contents

What is UVM?
uvm_component vs uvm_object
UVM Class Hierarchy
Naming Conventions
Reporting Macros
Hello UVM Testbench
UVM Phasing Overview
Running UVM Tests

1. What is UVM?

UVM is a SystemVerilog class library standardized as IEEE 1800.2. It builds on earlier methodologies (Cadence OVM, Synopsys VMM) and provides:

Base classes for every testbench role: test, environment, agent, driver, monitor, scoreboard, sequence
Phasing: an ordered set of functions/tasks (build, connect, run, check, report) executed in sync across all components
Factory: a registry that lets you override any component or object class at runtime without editing code
Configuration database (uvm_config_db): passes configuration and virtual interfaces down the hierarchy
TLM ports: standardized transaction-level communication between components
Reporting: hierarchical message system with ID, severity, and verbosity filtering

IEEE 1800.2: The UVM standard is maintained by Accellera. All major simulators (Questa, VCS, Xcelium) ship a compatible UVM library. Include it with: `include "uvm_macros.svh" and import uvm_pkg::*;

2. uvm_component vs uvm_object

This is the most fundamental distinction in UVM architecture:

// uvm_component — structural, persistent, has phases
// Lives in the hierarchy with a permanent path name
class my_driver extends uvm_driver #(my_item);
  // Registration macro — required for factory
  `uvm_component_utils(my_driver)

  // Always pass parent in constructor
  function new(string name = "my_driver", uvm_component parent = null);
    super.new(name, parent);
  endfunction

  // Phase methods — called by UVM infrastructure
  virtual function void build_phase(uvm_phase phase);
    super.build_phase(phase);
  endfunction

  virtual task run_phase(uvm_phase phase);
    // stimulus logic here
  endtask
endclass

// uvm_object — transient data, no hierarchy, no phases
// Created and destroyed dynamically during the test
class my_item extends uvm_sequence_item;
  `uvm_object_utils_begin(my_item)
    `uvm_field_int(addr,  UVM_ALL_ON)
    `uvm_field_int(data,  UVM_ALL_ON)
    `uvm_field_int(write, UVM_ALL_ON)
  `uvm_object_utils_end

  rand logic [31:0] addr;
  rand logic [31:0] data;
  rand logic        write;

  function new(string name = "my_item");
    super.new(name);    // no parent — objects have no hierarchy
  endfunction
endclass

Property	uvm_component	uvm_object
Base class	uvm_component → uvm_report_object → uvm_object	uvm_object directly
Constructor	new(name, parent)	new(name)
Hierarchy	Fixed path in TB tree	No hierarchy position
Phases	Yes — build, connect, run…	No phases
Lifetime	Entire simulation	Created/deleted dynamically
Examples	Driver, Monitor, Agent, Env, Test	Sequence item, Sequence, Config obj

3. UVM Class Hierarchy

4. UVM Naming Conventions

UVM library classes always start with uvm_ (e.g., uvm_driver, uvm_env)
User-defined classes use a project prefix: my_driver, uart_agent, apb_env
Files follow the class name: my_driver.sv, uart_pkg.sv
Always use _utils macros for registration — never skip them or the factory won't work
Instance names (constructor first argument) use lowercase with underscores: "my_driver", "env"

5. Reporting Macros

UVM reporting replaces $display. Messages carry ID strings, severity levels, and verbosity settings that can be filtered at runtime:

// `uvm_info — informational, filtered by verbosity
// Syntax: `uvm_info(ID_STRING, MESSAGE, VERBOSITY)
`uvm_info("DRV", $sformatf("Driving item: addr=%0h", item.addr), UVM_HIGH)
`uvm_info("TEST", "run_phase started", UVM_LOW)

// `uvm_warning — always printed, yellow in most simulators
`uvm_warning("MON", "Unexpected data seen on bus")

// `uvm_error — increments error count, simulation continues
`uvm_error("SCB", $sformatf("Data mismatch: exp=%0h got=%0h",exp,got))

// `uvm_fatal — stops simulation immediately
`uvm_fatal("CFG", "Virtual interface not set in config_db")

// Verbosity levels (highest detail → lowest):
// UVM_DEBUG (500) > UVM_HIGH (400) > UVM_MEDIUM (200)
// > UVM_LOW (100) > UVM_NONE (0)
// Default verbosity is UVM_MEDIUM — HIGH messages are hidden

Macro	Severity	Behavior
`uvm_info	UVM_INFO	Filtered by +UVM_VERBOSITY; no error count
`uvm_warning	UVM_WARNING	Always printed; increments warning count
`uvm_error	UVM_ERROR	Printed; increments error count; sim continues
`uvm_fatal	UVM_FATAL	Printed; immediately stops simulation

6. Hello UVM Testbench

The minimal complete UVM test: a test that extends uvm_test, builds nothing (no env yet), raises an objection in run_phase to keep simulation alive, prints a message, then drops the objection to end:

// hello_test.sv — minimal UVM test
`include "uvm_macros.svh"
import uvm_pkg::*;

class hello_test extends uvm_test;
  `uvm_component_utils(hello_test)

  function new(string name = "hello_test", uvm_component parent = null);
    super.new(name, parent);
  endfunction

  virtual function void build_phase(uvm_phase phase);
    super.build_phase(phase);
    `uvm_info("HELLO", "build_phase: constructing testbench", UVM_LOW)
    // In a real test, create env here:
    // env = my_env::type_id::create("env", this);
  endfunction

  virtual task run_phase(uvm_phase phase);
    // ALWAYS: raise before any time passes, drop at end
    phase.raise_objection(this, "Starting Hello UVM test");

    `uvm_info("HELLO", "Hello from UVM run_phase!", UVM_LOW)
    #100;  // simulate 100 time units of "activity"
    `uvm_info("HELLO", "run_phase complete", UVM_LOW)

    phase.drop_objection(this, "Hello UVM test done");
  endtask
endclass

// tb_top.sv — top-level module
module tb_top;
  `include "uvm_macros.svh"
  import uvm_pkg::*;
  import hello_test_pkg::*;

  initial begin
    // run_test() hands control to UVM — test selected by +UVM_TESTNAME
    run_test();
  end
endmodule

Always raise/drop objections: Without raise_objection, the run_phase completes at time 0 and the simulation ends immediately, even if you have delays in run_phase. This is the most common UVM beginner mistake.

7. UVM Phasing Overview

UVM phases execute in order across all components. Time-consuming phases (tasks) are synchronized via objections. Function phases complete before any component starts the next phase:

// All function phases (zero simulation time):
// build_phase     — top-down: create child components
// connect_phase   — bottom-up: wire TLM ports
// end_of_elaboration_phase — final config checks
// start_of_simulation_phase — print topology, etc.

// Time-consuming task phases:
// run_phase       — all components run concurrently
// (12 fine-grain sub-phases within run: reset, configure,
//  main, shutdown, etc. — used for precise ordering)

// Post-simulation function phases:
// extract_phase   — extract data from DUT/monitors
// check_phase     — compare expected vs actual
// report_phase    — print summary
// final_phase     — close files, databases

class my_component extends uvm_component;
  `uvm_component_utils(my_component)

  function void build_phase(uvm_phase phase);
    super.build_phase(phase);
    // create children, get config
  endfunction

  function void connect_phase(uvm_phase phase);
    // connect TLM ports between components
  endfunction

  task run_phase(uvm_phase phase);
    // stimulus, monitoring — runs concurrently with all others
  endtask

  function void check_phase(uvm_phase phase);
    // verify expected queue is empty, etc.
  endfunction

  function void report_phase(uvm_phase phase);
    `uvm_info("RPT", $sformatf("Total transactions: %0d", cnt), UVM_NONE)
  endfunction
endclass

8. Running UVM Tests

// Questa/ModelSim
vsim -do 'run -all' +UVM_TESTNAME=hello_test +UVM_VERBOSITY=UVM_HIGH tb_top

// VCS
vcs -sverilog -ntb_opts uvm tb_top.sv
simv +UVM_TESTNAME=hello_test +UVM_VERBOSITY=UVM_MEDIUM

// Xcelium
xrun -uvm tb_top.sv +UVM_TESTNAME=hello_test

// Common plusargs:
// +UVM_TESTNAME=<class_name>   — which test class to run
// +UVM_VERBOSITY=UVM_HIGH      — message verbosity level
// +UVM_TIMEOUT=10000000,YES    — override default timeout
// +UVM_MAX_QUIT_COUNT=5        — stop after 5 errors
// +uvm_set_config_int=uvm_test_top.env.agent,is_active,1

Key Takeaways — Day 6

UVM = IEEE 1800.2 — industry-standard SV class library for reusable testbenches
uvm_component: structural, hierarchical, has phases — drivers, monitors, agents, envs, tests
uvm_object: transient data, no phases — sequence items, sequences, config objects
Registration macros: `uvm_component_utils / `uvm_object_utils are mandatory for factory to work
Phasing: build→connect→run→check→report — ordered execution across all components
Objections: raise before activity, drop when done — controls when simulation ends
+UVM_TESTNAME: selects test at runtime — no recompilation needed to run a different test

Next → Day 07

UVM Testbench Architecture

Agent, driver, monitor, scoreboard, TLM analysis ports — building a complete, connected UVM environment.

→