Verilog System Tasks & Functions

initial begin
  $display("Time=%0t a=%b b=%b", $time, a, b); // prints now
  $write("hex=%h ", data);                        // no newline
  $write("dec=%0d\n", data);                      // manual newline
end

// $strobe — see settled NBA values
always @(posedge clk)
  $strobe("t=%0t q=%h", $time, q);  // prints after q<= updates

// $monitor — one active at a time
initial
  $monitor("t=%0t a=%b b=%b sum=%h", $time, a, b, sum);

// $timeformat(units, precision, suffix, width)
initial $timeformat(-9, 2, " ns", 10);
// -9 = nanoseconds, 2 decimal places, " ns" suffix, 10 chars wide
initial $display("t=%t", $time);  // e.g. "t=    100.00 ns"

`timescale 1ns/1ps

initial begin
  #10.5;
  $display("$time    = %0t", $time);    // 10 (truncated to ns)
  $display("$realtime= %f", $realtime); // 10.500000
end

$finish;        // exit simulator — use in automated regression
$finish(0);     // exit quietly (no time/location message)
$finish(2);     // exit with full diagnostic message

$stop;          // suspend; drop into interactive debug mode
$stop(0);      // suspend quietly

$info   ("Simulation started at t=%0t", $time);   // informational
$warning("Unexpected X on bus at t=%0t", $time); // warning, continues
$error  ("FAIL: expected %h got %h", exp, got);  // error, continues
$fatal  ("Unrecoverable error — aborting");       // error + $finish

// $random returns signed 32-bit
data = $random;            // any signed 32-bit value
data = {$random} % 256;   // unsigned 0–255
data = $random % 16;     // signed -15 to +15 (watch for negatives)

// Seed for reproducibility
integer seed = 42;
data = $random(seed);     // reproducible sequence from seed

// Random testbench pattern
integer i;
initial begin
  for (i=0; i<100; i++) begin
    @(posedge clk);
    data_in <= {$random} % 256;   // random 8-bit value
    addr    <= {$random} % 16;    // random 4-bit address
  end
end

integer fh;   // file handle

initial begin
  fh = $fopen("results.txt", "w");  // open for write
  if (fh == 0) begin
    $error("Cannot open results.txt");
    $finish;
  end

  $fdisplay(fh, "Simulation log — %0t", $time);
  $fwrite  (fh, "data=%h\n", data);

  $fclose(fh);
  $finish;
end

reg [7:0] rom [0:255];   // 256-byte ROM

initial begin
  $readmemh("program.hex", rom);           // fill [0:255]
  $readmemh("program.hex", rom, 0, 127);   // fill only [0:127]
  $readmemb("init.bin", rom);              // binary version
end

// program.hex
A5 3C 00 FF 12 AB CD EF
10 20 30 40 50 60 70 80
// @address can skip to an offset
@10 DE AD BE EF

initial begin
  $dumpfile("wave.vcd");          // output VCD filename
  $dumpvars(0, tb_top);           // 0=all levels, tb_top=scope
  $dumpvars(1, tb_top.dut);      // 1=top level of dut only
  $dumpvars(0, tb_top.dut.clk);  // specific signal
end

// Pause/resume dump for a specific window
initial begin
  #1000;
  $dumpoff;   // stop recording
  #500;
  $dumpon;    // resume recording
  $dumpall;   // force dump of current state
end

parameter DEPTH = 1024;
parameter ADDR_W = $clog2(DEPTH);  // = 10 — auto-size the address bus

reg [7:0] a = 8'hFF;
initial begin
  $display("unsigned: %0d", a);           // 255
  $display("signed:   %0d", $signed(a));   // -1
end