How does a CMOS inverter work?

A CMOS inverter uses a PMOS transistor (pull-up) and an NMOS transistor (pull-down) in series between VDD and GND. When the input is HIGH, the NMOS conducts pulling the output to GND. When the input is LOW, the PMOS conducts pulling the output to VDD. At any stable state, exactly one transistor is conducting — eliminating static power dissipation.

What is the difference between NMOS and PMOS?

NMOS turns ON when gate voltage exceeds the threshold (Vgs > Vth, typically +0.3–0.7V). PMOS turns ON when gate voltage falls below its threshold (Vgs < Vtp, typically negative). NMOS is approximately 2–3× faster than PMOS because electrons have higher mobility than holes in silicon.

Why does CMOS consume power only during switching?

In stable CMOS logic, either the PMOS or NMOS is OFF, creating no DC path from VDD to GND — zero static power. Power is only consumed during transitions when both transistors are briefly conducting simultaneously, and when charging/discharging the output capacitance: P = α·C·V²·f.

How is a CMOS NAND gate designed?

A 2-input CMOS NAND gate has two PMOS transistors in parallel (pull-up network) and two NMOS transistors in series (pull-down network). Output is LOW only when both inputs are HIGH (both NMOS conduct to GND). For any other input combination, at least one PMOS conducts, pulling the output HIGH.

VLSI · CMOS Fundamentals

CMOS Logic Design

Q: Why does CMOS consume power only during switching?

In stable CMOS logic, either the PMOS or NMOS is OFF, creating no DC path from VDD to GND — zero static power. Power is only consumed during transitions when both transistors are briefly conducting simultaneously, and when charging/discharging the output capacitance: P = α·C·V²·f.

Q: How is a CMOS NAND gate designed?

A 2-input CMOS NAND gate has two PMOS transistors in parallel (pull-up network) and two NMOS transistors in series (pull-down network). Output is LOW only when both inputs are HIGH (both NMOS conduct to GND). For any other input combination, at least one PMOS conducts, pulling the output HIGH.

Every digital gate in a modern VLSI chip — from a simple inverter to a billion-transistor AI accelerator — is built from complementary pairs of NMOS and PMOS transistors. Understanding CMOS logic is the foundation of all VLSI design.

1. MOSFET Fundamentals

The Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) is the fundamental building block of CMOS logic. It is a voltage-controlled switch — the gate voltage controls whether current can flow between source and drain.

NMOS (n-channel)

ON when V_gs > V_tn (positive threshold ~0.3–0.7V). Conducts electrons. Faster — used in pull-down networks (PDN). Gate HIGH → drain-source path conducts.

PMOS (p-channel)

ON when V_gs < V_tp (negative threshold ~−0.3 to −0.7V). Conducts holes. Slower (~2–3×). Used in pull-up networks (PUN). Gate LOW → drain-source path conducts.

Operating regions: A MOSFET operates in one of three regions depending on V_gs and V_ds: cut-off (off, V_gs < Vt), linear/triode (on, like a resistor), or saturation (on, constant current — used for current drive).

I_D = (μn · Cox/2) · (W/L) · (V_gs − Vt)² [saturation]

Drain current in saturation — controlled by W/L ratio, carrier mobility μ, and gate overdrive (V_gs − Vt)

2. The CMOS Inverter

The CMOS inverter is the simplest and most important gate. It pairs one PMOS (pull-up) and one NMOS (pull-down) transistor in series between VDD and GND, with their gates tied together at the input and drains tied together at the output.

Input (A)	PMOS State	NMOS State	Output (Y = A')	DC Path?
0 (GND)	ON (V_gs = −VDD, below Vtp)	OFF (V_gs = 0 < Vtn)	1 (VDD)	None — zero static power
1 (VDD)	OFF (V_gs = 0, above Vtp)	ON (V_gs = VDD > Vtn)	0 (GND)	None — zero static power
Transition	Both briefly ON	Both briefly ON	—	Brief: short-circuit current spike

Noise margins: The inverter has a voltage transfer characteristic (VTC) that defines input HIGH/LOW thresholds. Noise margin HIGH (NMH) and LOW (NML) quantify how much noise the circuit tolerates while still outputting valid logic levels. Ideal CMOS: NMH = NML = VDD/2.

3. CMOS Complex Gate Design

Any static CMOS gate follows the dual-network principle: a Pull-Up Network (PUN) of PMOS connects output to VDD for logic conditions that should produce a HIGH output; a Pull-Down Network (PDN) of NMOS connects output to GND for logic conditions that should produce LOW. The PUN and PDN are always structurally complementary (series↔parallel).

NAND Gate (2-input)

PDN: 2 NMOS in series (Y=0 only when A=1 AND B=1)
PUN: 2 PMOS in parallel (Y=1 whenever A=0 OR B=0)
Expression: Y = (A·B)' = NAND(A,B)

NOR Gate (2-input)

PDN: 2 NMOS in parallel (Y=0 when A=1 OR B=1)
PUN: 2 PMOS in series (Y=1 only when A=0 AND B=0)
Expression: Y = (A+B)' = NOR(A,B)

Design rule: In CMOS PDN, series transistors implement AND logic. In CMOS PUN, series transistors implement OR logic (De Morgan's theorem). The size of NMOS in series must be increased proportionally to maintain equal drive strength: W_series = n × W_single, where n is the stack depth.

4. CMOS Process Nodes & Scaling

Moore's Law describes the historical doubling of transistors per chip every ~2 years. This is achieved by shrinking the transistor's channel length (the "node" number: 28nm, 7nm, 3nm, etc.).

What Scales	Benefit	Challenge at Scale
Gate length (L)	Faster switching, more transistors per mm²	Short-channel effects, higher leakage
VDD	Lower dynamic power (P ∝ V²)	Reduced noise margins, harder timing closure
Gate oxide (tox)	Higher gate capacitance → faster switching	Gate tunneling leakage (solved with high-k dielectrics)
Wire pitch	More routing resources per area	Higher RC delay, electromigration at narrow wires

Interactive CMOS Labs

Explore MOSFET operation, the CMOS inverter, and stick diagrams with live simulations.

NMOS Bias Control

Gate Voltage V_gs

0.0 V

Transistor State

OFF (Cut-off)

When V_gs > Vth (~0.7V), gate charge repels holes and attracts electrons in the P-substrate, forming an inversion layer (N-channel) between source and drain.

Inverter Control

Input (A)

PMOS (Pull-Up)

ON — conducting

NMOS (Pull-Down)

OFF — open

Output (Y = A')

1

No DC path in either stable state → zero static power dissipation.

Stick Diagram Rules

Red (Poly) crossing Green (n-diff) forms an NMOS transistor.

Red (Poly) crossing Yellow (p-diff) forms a PMOS transistor.

Blue (Metal) lines are interconnects — crossing other layers does NOT create a transistor.

Black squares are contacts — required to connect metal to diffusion or metal to poly.

Euler path: For complex gates, a common gate ordering allows contiguous diffusion regions, minimizing area.

FAQ

A CMOS inverter pairs a PMOS (pull-up) and NMOS (pull-down) in series between VDD and GND. When input is HIGH, NMOS conducts pulling output to GND; PMOS is OFF. When input is LOW, PMOS conducts pulling output to VDD; NMOS is OFF. In stable state, exactly one transistor conducts — eliminating static DC power dissipation.

NMOS turns ON when V_gs exceeds the threshold voltage Vtn (~+0.3–0.7V). PMOS turns ON when V_gs falls below its threshold Vtp (~−0.3 to −0.7V). NMOS is approximately 2–3× faster than PMOS because electrons (NMOS carriers) have higher mobility in silicon than holes (PMOS carriers). NMOS is used for pull-down networks; PMOS for pull-up networks.

In any stable CMOS logic state, either the NMOS or PMOS is OFF — there is no DC path from VDD to GND. Power is consumed only during transitions when both transistors are briefly conducting simultaneously (short-circuit current) and when the output capacitance is charged/discharged: P = α·C·V²·f. This is why CMOS replaced NMOS and PMOS-only logic for all digital designs.

A 2-input CMOS NAND gate has two PMOS in parallel (pull-up) and two NMOS in series (pull-down). Output is LOW only when both inputs are HIGH — both NMOS conduct forming a path to GND. For any other combination, at least one PMOS conducts pulling output HIGH. The dual-network principle: PDN series = AND logic; PUN parallel = OR logic (De Morgan's complement).