EcrioniX Labs

DFT SCAN CHAINS

Design For Testability: Internal Scan Architecture

Current Operation
SHIFTING
TEST MODE (SE=1)

Test Controller

1 (Shift)

SE=1: Connects FFs into a shift register (Test).
SE=0: Connects FFs to logic clouds (Functional).

0

Standard DFT Procedure

  1. Shift In: Set SE=1. Pulse clock 3 times to load a test pattern (e.g., 101) into the chain.
  2. Capture: Set SE=0. Pulse clock once. The logic clouds process the pattern and save the result back to FFs.
  3. Shift Out: Set SE=1. Pulse clock 3 times to read the result at SCAN OUT.
  4. Compare: If output matches expected simulation, chip is good!
SCAN CHAIN SCHEMATIC
MUX 0 D Q LOGIC 0 LOGIC 0 LOGIC SE SI SCAN OUT
ACTIVE PATH
INACTIVE PATH