Day 6 put chiplets side by side on an interposer. Day 7 stacks them directly on top of one another — no interposer required for the die-to-die connection itself. The technology that makes this practical at scale is hybrid bonding, and it's a genuinely different mechanism from anything covered so far: it doesn't use bumps at all.
Where 2.5D packaging places chiplets next to each other on a shared interposer, 3D packaging stacks one die directly on top of another, connecting them face-to-face or face-to-back through the die surfaces themselves. This isn't mutually exclusive with 2.5D — a real package can combine both, stacking chiplets in 3D and placing that stack on a 2.5D interposer alongside other components (exactly what Day 6's CoWoS-L example does with HBM stacks).
Every packaging technology covered through Day 6 relies on bumps — small balls or pillars of solder or metal that physically and electrically join two surfaces. Hybrid bonding removes bumps from the equation entirely:
The result is a bond that is simultaneously the mechanical attachment between the two dies and the electrical connection between them — there's no separate bump structure taking up space, which is exactly why hybrid bonding can achieve such dramatically finer pitch than bump-based approaches.
| Technology | Pitch | Density / Notes |
|---|---|---|
| Traditional flip-chip micro-bump | 10–50 µm | General range for bump-based bonding |
| Original Foveros (e.g. Lakefield) | 50 µm | Face-to-face micro-bumps, ~400 connections/mm² |
| Foveros Direct | Sub-10 µm (targeting sub-5 µm, 18A-PT, H2 2026) | Direct Cu-Cu hybrid bonding replaces micro-bumps |
| TSMC SoIC (HVM, Feb 2026) | 6 µm | Hybrid bonding, F2F or F2B configurations |
| TSMC SoIC-Next (2027 target) | 3 µm | Next-generation hybrid bonding pitch |
Figures per TSMC and Intel technical disclosures and industry packaging coverage, current as of early 2026.
It's easy to conflate these, but they're mechanically different: original Foveros (used in products like Lakefield) bonds dies face-to-face through 50µm copper micro-bumps — still a bump-based technology, just a fine one. Foveros Direct replaces those micro-bumps entirely with direct copper-to-copper hybrid bonding, which is what actually unlocks the sub-10µm (and soon sub-5µm) pitch. Same brand name, genuinely different bonding mechanism underneath.
SoIC (System on Integrated Chips) is TSMC's hybrid-bonding 3D stacking technology. Unlike CoWoS (Day 6), SoIC needs no interposer for the die-to-die bond itself — the dies bond directly to each other. SoIC supports both face-to-face (F2F) and face-to-back (F2B) orientations, giving designers flexibility in how a stack of more than two dies is physically arranged.
AMD's 3D V-Cache is the clearest production example of hybrid bonding delivering a real, shipping performance advantage. It uses TSMC SoIC to bond an SRAM cache chiplet directly on top of a compute die, using the same two-phase process described above — dielectric-to-dielectric bonding at room temperature, then an anneal step that forms the copper-to-copper bonds through solid-state diffusion. AMD's own figures put the resulting interconnect density at roughly 200× that of a conventional 2D chiplet connection — a direct, measurable consequence of eliminating bumps.
Why this matters beyond cache: the same mechanism that lets AMD stack a cache die on a compute die applies to stacking compute-on-compute, compute-on-memory, or any two dies where extremely short, extremely dense vertical connections matter more than the flexibility of a 2.5D interposer.
Hybrid bonding's fine pitch creates a manufacturing requirement that's easy to overlook: two wafers or dies have to be mechanically aligned to an accuracy far finer than the bond pitch itself. A common rule of thumb is that bonding equipment needs alignment accuracy of roughly 0.1 to 0.25× the pad diameter — for a 1µm bond pad, that means alignment within 100 to 250 nanometers. Current wafer-to-wafer bonders can already achieve sub-50nm alignment, and next-generation equipment is pushing further: one 2026 bonding tool integrates X-ray metrology directly into the bonder head, measuring relative die-to-wafer position in real time and correcting alignment on the fly.
Despite everything in this lesson favoring hybrid bonding, the leading HBM manufacturers — SK hynix, Micron, and Samsung — are widely expected to stay with conventional microbumps for the mainstream HBM4 generation, rather than adopting full hybrid bonding immediately. Hybrid bonding's alignment and yield requirements are demanding enough that even at the cutting edge of memory stacking, the industry is choosing to defer the transition. That said, this isn't a rejection of the technology — as of April 2026, SK Hynix has completed 12-high HBM hybrid bonding validation as a parallel R&D track intended for future generations, once the manufacturing ecosystem matures further.
This is a useful, grounded contrast to the AMD 3D V-Cache case study above: hybrid bonding is real and shipping where the economics and yield maturity support it (cache-on-compute stacking), but even the companies most likely to benefit from it are moving carefully rather than rushing to replace microbumps everywhere at once.