Day 6 put chiplets side by side on an interposer. Day 7 stacks them directly on top of one another — no interposer required for the die-to-die connection itself. The technology that makes this practical at scale is hybrid bonding, and it's a genuinely different mechanism from anything covered so far: it doesn't use bumps at all.
3D vs 2.5D — Stacking Instead of Sitting Side by Side
Where 2.5D packaging places chiplets next to each other on a shared interposer, 3D packaging stacks one die directly on top of another, connecting them face-to-face or face-to-back through the die surfaces themselves. This isn't mutually exclusive with 2.5D — a real package can combine both, stacking chiplets in 3D and placing that stack on a 2.5D interposer alongside other components (exactly what Day 6's CoWoS-L example does with HBM stacks).
Hybrid Bonding — No Bumps at All
Every packaging technology covered through Day 6 relies on bumps — small balls or pillars of solder or metal that physically and electrically join two surfaces. Hybrid bonding removes bumps from the equation entirely:
Both die surfaces are planarized to atomic flatness — polished essentially perfectly smooth
The dies are brought into direct contact; a dielectric-to-dielectric bond forms between the oxide surfaces at room temperature
An anneal (controlled heating step) causes the copper pads embedded in each surface to bond directly to each other through solid-state diffusion — genuine copper-to-copper metallic bonds, not solder joints
The result is a bond that is simultaneously the mechanical attachment between the two dies and the electrical connection between them — there's no separate bump structure taking up space, which is exactly why hybrid bonding can achieve such dramatically finer pitch than bump-based approaches.
Bump Pitch — The Numbers That Matter
Technology
Pitch
Density / Notes
Traditional flip-chip micro-bump
10–50 µm
General range for bump-based bonding
Original Foveros (e.g. Lakefield)
50 µm
Face-to-face micro-bumps, ~400 connections/mm²
Foveros Direct
Sub-10 µm (targeting sub-5 µm, 18A-PT, H2 2026)
Direct Cu-Cu hybrid bonding replaces micro-bumps
TSMC SoIC (HVM, Feb 2026)
6 µm
Hybrid bonding, F2F or F2B configurations
TSMC SoIC-Next (2027 target)
3 µm
Next-generation hybrid bonding pitch
Figures per TSMC and Intel technical disclosures and industry packaging coverage, current as of early 2026.
Foveros vs Foveros Direct — Not the Same Technology
It's easy to conflate these, but they're mechanically different: original Foveros (used in products like Lakefield) bonds dies face-to-face through 50µm copper micro-bumps — still a bump-based technology, just a fine one. Foveros Direct replaces those micro-bumps entirely with direct copper-to-copper hybrid bonding, which is what actually unlocks the sub-10µm (and soon sub-5µm) pitch. Same brand name, genuinely different bonding mechanism underneath.
TSMC SoIC — Face-to-Face and Face-to-Back
SoIC (System on Integrated Chips) is TSMC's hybrid-bonding 3D stacking technology. Unlike CoWoS (Day 6), SoIC needs no interposer for the die-to-die bond itself — the dies bond directly to each other. SoIC supports both face-to-face (F2F) and face-to-back (F2B) orientations, giving designers flexibility in how a stack of more than two dies is physically arranged.
Case Study — AMD 3D V-Cache
AMD's 3D V-Cache is the clearest production example of hybrid bonding delivering a real, shipping performance advantage. It uses TSMC SoIC to bond an SRAM cache chiplet directly on top of a compute die, using the same two-phase process described above — dielectric-to-dielectric bonding at room temperature, then an anneal step that forms the copper-to-copper bonds through solid-state diffusion. AMD's own figures put the resulting interconnect density at roughly 200× that of a conventional 2D chiplet connection — a direct, measurable consequence of eliminating bumps.
Why this matters beyond cache: the same mechanism that lets AMD stack a cache die on a compute die applies to stacking compute-on-compute, compute-on-memory, or any two dies where extremely short, extremely dense vertical connections matter more than the flexibility of a 2.5D interposer.
🎯 Day 7 Key Takeaways
3D packaging stacks dies directly on top of each other; it can be combined with 2.5D interposers in the same package (as CoWoS-L does with HBM)
Hybrid bonding eliminates bumps: planarized surfaces, dielectric-to-dielectric bonding, then an anneal step forms direct copper-to-copper metallic bonds
Traditional micro-bumps run 10-50µm pitch (original Foveros: 50µm, ~400 connections/mm²); hybrid bonding runs sub-10µm (TSMC SoIC in HVM at 6µm as of Feb 2026, targeting 3µm by 2027)
Foveros and Foveros Direct are mechanically different — original Foveros uses micro-bumps, Foveros Direct uses true hybrid bonding
TSMC SoIC supports both face-to-face and face-to-back stacking, and needs no interposer for the die-to-die bond itself
AMD's 3D V-Cache (built on TSMC SoIC) achieves roughly 200x the interconnect density of a 2D chiplet connection — a real, shipping proof point
Frequently Asked Questions
What is hybrid bonding?
Hybrid bonding eliminates solder bumps entirely. Two die surfaces are planarized to atomic flatness, brought into contact, and form direct copper-to-copper metallic bonds where copper pads meet, while the surrounding dielectric (oxide) surfaces bond to each other, in a two-phase room-temperature-then-anneal process.
What is the difference between Foveros and Foveros Direct?
Original Foveros (used in products like Lakefield) uses face-to-face bonding through 50 micron pitch copper micro-bumps, yielding about 400 connections per square millimeter. Foveros Direct replaces those micro-bumps with direct copper-to-copper hybrid bonding, targeting a sub-10 micron pitch and, per Intel's 2026 roadmap, a sub-5 micron pitch on the 18A-PT node.
What is TSMC SoIC?
SoIC (System on Integrated Chips) is TSMC's hybrid-bonding-based 3D stacking technology. It uses direct copper-to-copper bonding instead of micro-bumps, supports both face-to-face and face-to-back die orientations, and reached high-volume manufacturing at a 6 micron bond pitch as of February 2026, with a 3 micron 'SoIC-Next' generation targeted for 2027.
What real product uses TSMC SoIC hybrid bonding?
AMD's 3D V-Cache technology uses TSMC SoIC to bond an SRAM cache chiplet directly on top of a compute die using copper-to-copper hybrid bonding rather than solder micro-bumps, achieving roughly 200 times the interconnect density of a conventional 2D chiplet connection.
How much finer is hybrid bonding pitch compared to traditional micro-bumps?
Traditional flip-chip micro-bump bonding is typically limited to a 10-50 micron pitch. Hybrid bonding achieves sub-10 micron pitch today, with TSMC already in high-volume manufacturing at 6 microns and both TSMC and Intel targeting 3-5 micron pitches within their near-term roadmaps.