Days 6 and 7 covered how chiplets get bonded together. Day 8 covers the question that determines whether any of it is worth doing: how do you know a chiplet works before you've permanently bonded it to three or eleven others? Once hybrid-bonded, there is no rework. This lesson is about the economics and engineering of testing chiplets before that point of no return.
A monolithic die that fails test is scrapped — one wasted die. A multi-chiplet package is a different story entirely: once chiplets are joined via micro-bumps or hybrid bonding, rework is impossible. If even one of several bonded chiplets turns out to be defective, the entire package — every good chiplet along with the bad one — gets scrapped. A hybrid-bonded stack in particular cannot be reheated and separated without destroying it.
The cost of catching a defect climbs steeply the later you catch it. A defect found at wafer-level die test is cheap to deal with — discard one die. The same defect discovered only after full packaging can cost roughly 10 to 100 times more, because it now takes the entire assembly, the bonding process, and every other good chiplet in that package down with it.
System yield across N independently-tested chiplets is approximately the product of each chiplet's individual yield. This compounds fast:
4-chiplet package, 95% known-good-die yield per chiplet: 0.95 ^ 4 = 0.8145 → ~81.5% composite yield AMD MI300X-scale package, 12 chiplets, 98% known-good-die yield per chiplet: 0.98 ^ 12 = 0.7847 → ~78.5% composite yield Even at a high 98% individual chiplet yield, stacking 12 of them still throws away roughly 1 in 5 completed packages.
This is the sharpest possible argument for rigorous pre-bond testing: the more chiplets you combine — exactly the strategy this course has spent seven days explaining the benefits of — the more brutally individual chiplet defect rates compound against you at the package level, unless you catch bad die before they're ever bonded.
In practice, testing every die to the fullest possible standard isn't always economically feasible either — which is why the industry compromise term "Good Enough Die" exists: balancing test thoroughness and cost against the real fallout risk for a given product's chiplet count and value.
| Stage | When | What It Checks |
|---|---|---|
| Pre-bond wafer sort (EWS) | Before any assembly | Electrical Wafer Sort tests each die on the wafer, sorting known-good die before they're ever diced and bonded |
| Known-Good-Stack (KGS) test | After 3D stacking, before final packaging | Verifies the bonded stack as a unit — catching bonding-process defects that individual pre-bond tests couldn't see |
| Final (post-package) test | After complete assembly | Validates the fully packaged part before it ships to a customer |
Testing at fine bump or hybrid-bond pitch runs into a physical wall: the pads are simply too small and too closely spaced for conventional test probes to touch directly. This is exactly the same class of problem as any other design-for-test challenge — you need built-in structures (scan chains, BIST, boundary-scan-style access) designed into the chiplet from the start, because you cannot rely on external probing once the pitch gets fine enough.
IEEE P1838 is the industry's answer at the standards level: a test access architecture standard for 2.5D, 3D, and 5.5D stacked integrated circuits, defining how test signals reach into chiplets whose physical connections can't be probed directly, so pre-bond, post-bond, and stack-level testing can all be coordinated through a common, standardized access scheme rather than a different bespoke solution per product.