Phase 2 covered the physical technology chiplets bond, thermal-manage, and power through. Phase 3 opens with the question every physical design engineer eventually faces: how do you actually floorplan a design that no longer fits on one die? The honest answer is that floorplanning itself changes shape — from placing cells on a die to co-designing dies and package together.
Monolithic floorplanning is a single-domain problem: place macros, route power, minimize congestion, all within one die's boundary. Chiplet-aware floorplanning adds a second, coupled domain on top of that: the package or interposer layout that determines how the dies relate to each other physically. These two domains aren't sequential — a decision made in the package layout (where a chiplet sits, how far it is from its neighbor) directly constrains what's achievable in that chiplet's own floorplan, and vice versa.
Before any macro gets placed, chiplet-based design forces a decision monolithic design never required: which logic goes on which die? Multi-die partitioning and co-optimization tools let architects explore this under a specific set of competing constraints:
Get partitioning wrong, and no amount of floorplanning skill downstream can fix it — a poorly partitioned design bakes in excess die-to-die traffic, awkward power delivery, or thermal hot spots that no later optimization pass can undo.
EDA tools now include co-design capabilities that concurrently handle chip floorplans and the package/interposer layout, precisely because decisions in one domain affect the other. Floorplanning a chiplet in isolation and handing the result to a package designer afterward is the sequential approach that chiplet-aware tools are explicitly built to replace — by the time a sequential handoff reveals a problem, both sides may need significant rework.
A recurring theme across chiplet-aware flows is the unified data model — keeping package-aware context present even while an engineer is designing an individual die, so that connectivity stays consistent once every chiplet is assembled onto the shared substrate. Without this, mismatches between a die's edge connections and the package's expected layout only surface late — exactly the kind of late-stage discovery that advanced packaging (Days 6-10) already makes expensive to fix.
3Dblox is TSMC's common abstraction format for representing 3D IC assemblies. It is not yet a formal IEEE standard, but has gained broad industry acceptance and support across major EDA vendors — giving chiplet-aware tools from different vendors a practical, shared way to describe a multi-die assembly's structure, rather than each tool inventing its own incompatible representation.
Partitioning and package co-design aren't the only forces shaping a chiplet floorplan — where you physically place each chiplet relative to its neighbors directly determines whether Day 9's hot-spot problem gets better or worse. This has become its own active research area, with several named algorithms specifically targeting it:
| Algorithm | Approach |
|---|---|
| TAP-2.5D | The first open-source thermally-aware chiplet placement methodology for heterogeneous 2.5D systems, jointly minimizing temperature and total wirelength |
| SP-CP | A wirelength-driven placer using a sequence-pair based tree with thermal-aware net weights |
| ATPlace2.5D | Trains a compact thermal model against the industry-standard HotSpot simulator, achieving a 2,575× speedup versus running full HotSpot simulation directly |
The underlying principle across all of them is straightforward to state, even though it's hard to optimize automatically: avoid placing multiple high-power chiplets so their hot spots stack vertically across tiers, and deliberately use whitespace or extra chiplet spacing as lateral heat-spreading paths rather than treating empty package area as pure waste. A floorplan that looks efficient on wirelength alone can still fail thermally if it stacks every hot block on top of every other hot block.
| Tool | Vendor | Capability |
|---|---|---|
| Integrity 3D-IC Platform | Cadence | Unified 3D design planning, implementation, and system analysis across custom analog, IC, and board domains |
| 3DIC Compiler | Synopsys | Multi-die/advanced package co-design: feasibility exploration, partitioning, prototyping, and floorplanning across the full stack |
Tool capabilities per Cadence and Synopsys product documentation.