Claude for DV Engineers

Write a complete SystemVerilog assertion module for a [PROTOCOL_NAME] interface with these signals:
  input logic clk, rst_n
  input logic req, ack, valid
  input logic [DATA_WIDTH-1:0] data

Protocol rules:
1. req must be followed by ack within 4 cycles
2. data must be stable while valid is high
3. ack cannot be asserted without a prior req
4. No back-to-back req without ack in between

Requirements:
- Use concurrent assertions with @(posedge clk) disable iff (!rst_n)
- Create named sequences for req_to_ack and data_stable
- Include a bind statement to attach to the DUT non-intrusively
- Add $info messages in the checker for passing assertions (useful for debug)

Write a complete AXI4-Lite protocol checker in SystemVerilog assertions. Cover:
- AWVALID/AWREADY handshake rules (valid must not drop without ready)
- WVALID/WREADY handshake
- BVALID/BREADY response timing (must respond within 16 cycles)
- ARVALID/ARREADY read address channel
- RVALID/RREADY data return
- BRESP and RRESP must be OKAY(2'b00) or SLVERR(2'b10) only
- No X/Z on control signals when valid is high

Use: module axi4lite_checker #(parameter TIMEOUT=16) with parameter for max latency.
Include bind statement for: bind [DUT_MODULE_NAME] axi4lite_checker chk_u(...)

Write a UVM sequence_item and two sequences for an [APB/AXI4/SPI] bus:

sequence_item (apb_transaction):
- rand logic [31:0] addr (constrained to valid range 0x0000_0000 - 0x0000_FFFF)
- rand logic [31:0] data
- rand logic [3:0]  strb (write byte enables)
- rand apb_dir_e    direction (READ, WRITE)
- rand int unsigned delay (1-10 cycles, weighted: 60% = 1-2 cycles)

Sequences:
1. apb_write_seq — 100 random writes
2. apb_targeted_seq — directed writes to addresses: 0x100, 0x104, 0x108 (covers register bank)

Use `uvm_object_utils_begin macros, call super.new() in constructor, define constraint blocks with meaningful names.

Write a complete UVM agent for an APB master interface using virtual interface (apb_if vif).

Include:
- apb_driver: extends uvm_driver, run_phase drives transactions onto vif, waits for PREADY
- apb_monitor: extends uvm_monitor, samples completed transactions and writes to analysis port
- apb_sequencer: extends uvm_sequencer (typedef only)
- apb_agent: extends uvm_agent, build_phase creates driver/monitor/sequencer based on is_active
- Connect sequencer-driver TLM in connect_phase

Use `uvm_component_utils, get_full_name() in messages, check vif != null in build_phase.

Write a UVM scoreboard for a [16-entry FIFO / register file / pipeline] DUT.

Requirements:
- Two uvm_analysis_imp ports: one from write-side monitor, one from read-side monitor
- Internal reference model: associative array [addr] -> data for register file, or queue for FIFO
- write_export: store expected data in reference model
- read_export: compare DUT output to expected, call `uvm_error on mismatch with full transaction details
- report_phase: print pass/fail summary with total checks and mismatches
- Handle X/Z comparison: a DUT output of X is always a failure

Use `uvm_analysis_imp_decl macros for multiple imp ports.

Write a UVM coverage collector (extends uvm_subscriber) for an APB interface covering:

Covergroup 1 - apb_transaction_cg:
- cp_direction: READ, WRITE
- cp_addr_range: bins low[0:0x1FF], mid[0x200:0x3FF], high[0x400:0x7FF]
- cp_data_corners: bins zero=0, all_ones=32'hFFFF_FFFF, other = default
- cross cp_direction, cp_addr_range

Covergroup 2 - apb_timing_cg:
- cp_wait_states: bins zero_wait=0, one_wait=1, multi_wait[2:5], long_wait[6:$]
- cp_back_to_back: bins yes=1, no=0 (consecutive transactions without idle)

Sample in write() function. Print coverage percentage in report_phase.

Here is my functional coverage report from Questa after 50K simulation cycles:

[PASTE YOUR COVERAGE REPORT TEXT HERE]

Tasks:
1. List all bins with 0 hits — categorize as: unreachable (by design), missing test, or constraint issue
2. For each uncovered bin, suggest a targeted UVM sequence or constraint modification to hit it
3. Identify any cross-coverage combinations that are structurally impossible
4. Suggest 3 additional coverpoints I should add that my current covergroups are missing

My design is: [brief description — e.g. "AXI4 slave with 8 registers, no burst support"]

My simulation has an assertion failure. Help me debug it.

Failing assertion:
[PASTE ASSERTION TEXT HERE]

Simulation log at failure time:
[PASTE LOG LINES HERE]

Signal values at T=[TIMESTAMP]ns:
  clk=1, rst_n=1, req=1, ack=0, valid=0, state=WAIT_ACK

My RTL state machine (relevant portion):
[PASTE RTL CODE HERE]

Questions:
1. What is the root cause of this failure?
2. Is this an RTL bug or a testbench bug?
3. What is the minimal fix?
4. What regression assertion should I add to prevent this from recurring?

Write SVA assertions for a 2-FF CDC synchronizer between clk_a (100MHz) and clk_b (83MHz):

Signals:
  input logic clk_a, clk_b, rst_n
  input logic data_a         // source domain
  input logic sync_q1, sync_q2  // synchronizer flops in clk_b domain
  output logic data_b_sync   // synchronized output

Assert:
1. data_a must be stable for at least 2 clk_a cycles before transitioning (no glitches)
2. data_b_sync must equal sync_q2 (structural check)
3. Metastability window: sync_q1 must not change within 0.5ns of clk_b rising edge (use $realtime)
4. Max synchronization latency from data_a to data_b_sync is 4 clk_b cycles

Use separate clocking blocks for each clock domain in the assertion module.

Write a UVM sequence targeting these uncovered corner cases for my FIFO DUT:

1. Write to FULL FIFO (wfull=1) — should be silently dropped
2. Read from EMPTY FIFO (rempty=1) — should return X
3. Simultaneous read and write at exact FIFO depth boundary (depth=15/16)
4. Burst write until full, then burst read until empty — back-to-back
5. Single write followed immediately by single read (depth oscillates 0→1→0)

For each case:
- Write a named sequence class (e.g. fifo_full_write_seq)
- Add assertions in the sequence body using `uvm_info to annotate what's being tested
- Specify the expected DUT behavior in a comment at the top

I'm verifying a [BLOCK NAME — e.g. AXI4 DMA controller]. Here is the block specification:

[PASTE SPEC SECTION OR DESCRIBE KEY FEATURES]

Generate a structured verification plan covering:
1. Feature list (each verifiable feature from the spec)
2. For each feature: verification method (directed, constrained-random, formal, or gate-level sim)
3. Coverpoints needed (what functional coverage to close)
4. SVA assertions needed (which protocol rules to encode)
5. Corner cases (the 10 most likely sources of RTL bugs in this block type)
6. Regression exit criteria (minimum coverage % and assertion pass rate)

Format as a table where possible.

Write formal verification properties (SVA) for a [FIFO / arbiter / FSM] suitable for JasperGold.

Requirements:
- Safety properties: things that must never happen (assert)
- Liveness properties: things that must eventually happen (assert ...eventually)
- Assumptions (assume) to constrain the formal environment
- Cover properties to verify reachability of key states

For the [BLOCK]:
- Safety: FIFO cannot overflow (wcount > DEPTH)
- Safety: Grant cannot go to two requestors simultaneously (arbiter)
- Liveness: Every request must eventually receive a grant (within 32 cycles)
- Assumption: rst is asserted for at least 2 cycles at startup

Make properties parametric where possible. Include a comment explaining what each property verifies and what bug it would catch.

Generate a UVM Register Abstraction Layer (RAL) model for these registers:

Base address: 0x4000_0000

| Offset | Name      | Width | Reset      | Access | Description               |
|--------|-----------|-------|------------|--------|---------------------------|
| 0x000  | CTRL      | 32    | 0x0000_0000| RW     | Control: [0]=enable, [1]=loopback, [7:4]=mode |
| 0x004  | STATUS    | 32    | 0x0000_0001| RO     | Status: [0]=ready, [31:1]=reserved |
| 0x008  | DATA_IN   | 32    | 0x0000_0000| WO     | Write data register       |
| 0x00C  | DATA_OUT  | 32    | 0x0000_0000| RO     | Read data register        |

Generate: individual register classes, reg_block class with build() method, map configuration.
Include a basic reg_sequence that reads STATUS, writes CTRL enable bit, then reads back.

[Use this prompt with Extended Thinking enabled — click the lightbulb icon in Claude.ai]

I have an intermittent simulation failure that only occurs at specific seed values.
The failure involves a timing race between [two clock domains / two FSMs / pipeline stages].

Here is the full simulation log for a failing seed:
[PASTE LOG]

Here is the RTL for the modules involved:
[PASTE RTL — up to 500 lines is fine with Extended Thinking]

The failure pattern: [describe when it happens — e.g. "assertion fires 847 cycles in, but only with seeds ending in 3"]

Please:
1. Trace the exact sequence of events leading to the failure
2. Identify whether this is a functional bug, constraint issue, or timing arc problem
3. Propose the minimal RTL change to fix it
4. Explain why other seeds don't trigger it

Write a gate-level simulation (GLS) testbench setup for my design:

DUT: [MODULE_NAME].v (gate-level netlist from synthesis)
SDF: timing.sdf (back-annotated delays from synthesis tool)
Technology cell library: [TECH_LIB].v

Requirements:
- Include `timescale 1ns/1ps
- Use $sdf_annotate("timing.sdf", dut_inst) for back-annotation
- Add $shm_open / $vcd_dumpfile for waveform capture
- Instantiate the gate-level netlist (not RTL)
- Initialize all flops with specific reset sequence: assert rst for 10 cycles
- Add supply voltage nets (VDD=1, VSS=0) if required by standard cells
- Show the compilation command for Questa: vlog -sv +define+GATE_SIM netlist.v tb.sv