What is the difference between compile and compile_ultra in Design Compiler?

compile performs standard logic synthesis with basic optimization. compile_ultra enables more aggressive algorithms including datapath optimization, register retiming, and better area recovery. Use compile_ultra -no_autoungroup to prevent DC from automatically flattening your hierarchy, which is important when you want to preserve module boundaries for downstream flows (STA, P&R).

How do I check timing after synthesis in Genus and DC?

In Genus: use report_timing to see the worst path, report_qor for a full quality summary including WNS/TNS/hold slack, and report_timing -nworst 10 to see the 10 worst paths. In Design Compiler: use report_timing -transition_time -nets -attributes -nosplit for detailed path analysis, and report_qor > syn.qor to save the quality report. Always check both setup (max) and hold (min) timing after synthesis.

How do I write a gate-level netlist in Genus and DC?

In Genus: write_hdl > netlist.v writes the mapped Verilog netlist. In Design Compiler: write -format verilog -hierarchy -output netlist.v exports the hierarchical netlist. Always use write_sdc to export the constraints alongside the netlist so downstream STA and P&R tools have the same timing intent.

What is report_qor and why is it important?

report_qor (Quality of Results) gives a one-shot summary of your synthesis quality: Worst Negative Slack (WNS), Total Negative Slack (TNS), number of violating paths, total cell area, total wire length estimate, and logic levels on critical paths. It is the first report to check after any synthesis run to quickly assess whether timing is met and whether further optimization is needed.

What does set_dont_touch and set_dont_use do in synthesis?

set_dont_touch prevents the synthesis tool from optimizing or modifying a specific instance or net — useful for preserving manually instantiated cells, test logic, or clock buffers. set_dont_use prevents the tool from using specific library cells during synthesis — commonly used to exclude slow cells, cells with high leakage, or cells not supported in your target technology corner.

Genus & DC Synthesis Commands Cheat Sheet — Cadence Genus / Synopsys Design Compiler

Q: What is the difference between syn_generic, syn_map, and syn_opt in Genus?

syn_generic performs technology-independent RTL optimization (converts RTL to generic Boolean logic). syn_map maps that logic onto actual library cells from your target technology. syn_opt performs incremental gate-level optimization after mapping — fixing timing violations, reducing area, and improving TNS. You can run all three separately or use 'synthesize -to_mapped' to run them in sequence.

Complete Genus Synthesis Flow

Run order: read_libs → read_hdl → elaborate → read_sdc → syn_generic → syn_map → syn_opt → reports → write_hdl

TCL — genus_flow.tcl

# ── 1. Library Setup ────────────────────────────────────────
set_db init_lib_search_path  "/tech/libs /tech/lef"
set_db init_hdl_search_path  "/src/rtl"
set_db library               {slow.lib fast.lib}
set_db lef_library            {tech.lef cells.lef}

# ── 2. Read RTL ──────────────────────────────────────────────
read_hdl -language verilog    top.v sub_a.v sub_b.v

# ── 3. Elaborate ─────────────────────────────────────────────
elaborate                     top_module
check_design -all
check_timing_intent -verbose

# ── 4. Constraints ───────────────────────────────────────────
read_sdc                      constraints.sdc

# ── 5. Synthesis ─────────────────────────────────────────────
set_db syn_global_effort      high
syn_generic
syn_map
syn_opt

# ── 6. Reports ───────────────────────────────────────────────
report_timing                 > reports/timing.rpt
report_qor                    > reports/qor.rpt
report_area                   > reports/area.rpt
report_power                  > reports/power.rpt

# ── 7. Output ────────────────────────────────────────────────
write_hdl                     > outputs/netlist.v
write_sdc                     > outputs/constraints_out.sdc
write_sdf                     > outputs/timing.sdf

Library & Environment Setup

Command	Example	Description
set_db init_lib_search_path	set_db init_lib_search_path "/tech/libs"	Directory where Genus searches for .lib / .lef files
set_db init_hdl_search_path	set_db init_hdl_search_path "/src/rtl"	Directory where Genus searches for HDL source files
set_db library	set_db library {slow.lib fast.lib}	Target technology library files (.lib)
set_db lef_library	set_db lef_library {tech.lef std_cells.lef}	LEF files for physical cell dimensions
set_db qrc_tech_file	set_db qrc_tech_file tech.tch	QRC tech file for RC parasitic extraction
set_db common_ui	set_db common_ui false	Run in legacy (non-unified) UI mode — required for some older scripts
report_libs	report_libs	List all loaded libraries and their attributes

Reading RTL & Elaboration

Command	Example	Description
read_hdl	read_hdl -language verilog top.v sub.v	Read Verilog/VHDL source files. Builds elaboration database
read_hdl -sv	read_hdl -sv design.sv	Read SystemVerilog files explicitly
read_hdl -vhdl	read_hdl -vhdl design.vhd	Read VHDL files
elaborate	elaborate top_module	Elaborate the top-level design — resolves hierarchy and parameters
elaborate -parameters	elaborate top -parameters {WIDTH 8}	Elaborate with parameter override
check_design -all	check_design -all	Run all design rule checks — reports undriven nets, unresolved refs
check_timing_intent	check_timing_intent -verbose	Verify SDC constraints are complete and consistent

Timing Constraints (SDC)

Best practice: Use read_sdc to load an external .sdc file rather than writing constraints inline — keeps scripts maintainable and reusable across tools.

Command	Example	Description
read_sdc	read_sdc constraints.sdc	Load SDC timing constraint file (recommended)
create_clock	create_clock -period 5 -name clk [get_ports clk]	Define a clock — 5 ns = 200 MHz
create_generated_clock	create_generated_clock -divide_by 2 -source clk clk_div2	Define a derived clock from an existing clock
set_input_delay	set_input_delay -clock clk -max 1.5 [all_inputs]	Input arrival time relative to clock edge (setup)
set_output_delay	set_output_delay -clock clk -max 1.0 [all_outputs]	Output required time relative to clock edge (setup)
set_clock_uncertainty	set_clock_uncertainty -setup 0.1 [get_clocks clk]	Add clock jitter / margin to timing analysis
set_clock_transition	set_clock_transition 0.05 [get_clocks clk]	Set clock edge transition time
set_dont_touch	set_dont_touch [get_cells u_clk_buf]	Prevent optimization of specific cell/net
set_dont_use	set_dont_use [get_lib_cells /SLOW]	Exclude specific library cells from synthesis
set_false_path	set_false_path -from [get_ports rst]	Mark path as non-timing-critical (async reset, test)
set_multicycle_path	set_multicycle_path 2 -setup -from [get_cells u_slow*]	Relax timing on paths that take multiple cycles
set_max_fanout	set_db [get_designs top] .max_fanout 16	Limit fanout — prevents excessive net loading

Synthesis Execution

Command	Example	Description
syn_generic	syn_generic	Technology-independent optimization — converts RTL to Boolean logic
syn_generic -physical	syn_generic -physical	Generic with physical awareness (needs floorplan DEF)
syn_map	syn_map	Technology mapping — maps generic logic to library cells
syn_opt	syn_opt	Post-map optimization — fixes timing, reduces area, improves TNS
syn_opt -incr	syn_opt -incr	Incremental optimization — faster, targets only violating paths
syn_opt -spatial	syn_opt -spatial	Physically-aware optimization using location data
synthesize -to_mapped	synthesize -to_mapped -effort high	Run full synthesis flow (generic+map+opt) in one command
set_db syn_global_effort	set_db syn_global_effort high	Set effort level: low / medium / high
set_db syn_generic_effort	set_db syn_generic_effort high	Effort for syn_generic stage specifically
set_db syn_map_effort	set_db syn_map_effort high	Effort for technology mapping stage
set_db syn_opt_effort	set_db syn_opt_effort high	Effort for post-map optimization stage
set_db tns_opto	set_db tns_opto true	Enable Total Negative Slack optimization (fixes more paths)
ungroup	ungroup -all -flatten	Flatten hierarchy for better cross-boundary optimization
group_path	group_path -name critical -weight 5 -critical_range 0.5	Group paths for targeted optimization effort

TCL — high-effort incremental

# Initial synthesis
set_db syn_global_effort high
set_db tns_opto true
syn_generic
syn_map
syn_opt

# If timing still fails — incremental pass
syn_opt -incr
report_timing -nworst 5

Reports & Analysis

Command	Example	Description
report_timing	report_timing > timing.rpt	Show worst setup timing path with slack
report_timing -nworst	report_timing -nworst 10	Show N worst timing paths
report_timing -hold	report_timing -hold -nworst 5	Show worst hold timing paths
report_timing -from -to	report_timing -from u_ctrl/state_reg -to u_out/d	Report specific start-to-endpoint path
report_qor	report_qor > qor.rpt	Quality of Results: WNS, TNS, area, logic levels — first check after synthesis
report_area	report_area -hier > area.rpt	Area breakdown by module hierarchy
report_power	report_power -hier > power.rpt	Dynamic + leakage power per module
report_gates	report_gates -hier	Cell count and gate types per module
report_clock_gating	report_clock_gating	Clock gating statistics — ICG cell count
report_dp	report_dp	Datapath component inference report (multipliers, adders)
report_units	report_units	Time/capacitance/resistance units in current design
report_design_rules	report_design_rules	DRC violations: max fanout, max transition, max cap
report_messages	report_messages -category WARNING	Show tool warnings/errors from synthesis run

Netlist & Output

Command	Example	Description
write_hdl	write_hdl > netlist.v	Write gate-level Verilog netlist
write_hdl -generic	write_hdl -generic > generic.v	Write post-generic (pre-map) netlist
write_sdc	write_sdc > out.sdc	Write back-annotated SDC constraints
write_sdf	write_sdf > timing.sdf	Write Standard Delay Format — used for gate-level sim
write_db	write_db -all_root_attributes design.db	Save full Genus design checkpoint for restore
read_db	read_db design.db	Restore a saved Genus checkpoint
write_do_lec	write_do_lec > lec.do	Generate Conformal LEC script for equivalence check
write_dft_atpg	write_dft_atpg -library atpg_lib	Write DFT netlist for Modus ATPG

DFT Commands

Command	Example	Description
check_dft_rules	check_dft_rules -verbose	Check design for DFT rule violations before scan insertion
define_scan_chain	define_scan_chain chain1 -head scan_in -tail scan_out	Define scan chain routing
connect_scan_chains	connect_scan_chains -auto_create_chains	Automatically connect scan chains
report_scan_setup	report_scan_setup	Report scan chain configuration
set_db dft_scan_style	set_db dft_scan_style muxed_scan	Set scan style: muxed_scan / lssd / clocked_scan

Complete DC Synthesis Flow

DC mode: Run dc_shell -f flow.tcl or start dc_shell interactively. Use dc_shell-t for Tcl-only mode (recommended for scripting).

TCL — dc_flow.tcl

# ── 1. Library Setup ────────────────────────────────────────
set_app_var search_path      ". /tech/db /tech/lef"
set_app_var target_library   "slow.db"
set_app_var link_library     "* $target_library"
set_app_var symbol_library   "generic.sdb"

# ── 2. Read & Elaborate ──────────────────────────────────────
analyze -format verilog       {top.v sub_a.v sub_b.v}
elaborate                     top_module
current_design                top_module
link
uniquify
check_design

# ── 3. Constraints ───────────────────────────────────────────
source                        constraints.tcl
# OR
create_clock -period 5        [get_ports clk]
set_input_delay  -clock clk -max 1.5  [all_inputs]
set_output_delay -clock clk -max 1.0  [all_outputs]

# ── 4. Synthesis ─────────────────────────────────────────────
compile_ultra -no_autoungroup

# ── 5. Reports ───────────────────────────────────────────────
report_timing -transition_time -nets -attributes -nosplit \
              > reports/timing.rpt
report_qor                    > reports/qor.rpt
report_area  -nosplit -hier    > reports/area.rpt
report_power -nosplit -hier    > reports/power.rpt

# ── 6. Output ────────────────────────────────────────────────
write -format verilog -hier   -output outputs/netlist.v
write -format ddc     -hier   -output outputs/design.ddc
write_sdc                     outputs/constraints_out.sdc
exit

Library & Environment Setup

Command	Example	Description
set_app_var search_path	set_app_var search_path ". /tech/db"	Directories DC searches for library .db files
set_app_var target_library	set_app_var target_library "slow.db"	Standard cell library used for synthesis (must be .db format)
set_app_var link_library	set_app_var link_library "* $target_library"	Libraries for linking. The * includes already-loaded designs
set_app_var symbol_library	set_app_var symbol_library "generic.sdb"	Symbol library for Design Vision schematic view
define_design_lib	define_design_lib WORK -path "./work"	Set working directory for compiled design objects
list_lib	list_lib	List all currently loaded libraries
report_lib	report_lib slow.db	Show library details — cells, timing arcs, operating conditions

Reading RTL & Elaboration

Command	Example	Description
analyze	analyze -format verilog {top.v sub.v}	Parse and analyze RTL files — preferred over read_verilog
read_verilog	read_verilog top.v	Read Verilog files directly (alternative to analyze+elaborate)
read_vhdl	read_vhdl design.vhd	Read VHDL source files
read_ddc	read_ddc design.ddc	Read a previously saved DDC checkpoint
elaborate	elaborate top_module	Build design hierarchy and resolve all references
elaborate -parameters	elaborate top -parameters {WIDTH=8}	Elaborate with parameter override
current_design	current_design top_module	Set active design context for all subsequent commands
link	link	Resolve all submodule references against loaded libraries
uniquify	uniquify	Create unique copies of multiply-instantiated modules
check_design	check_design	Validate design — reports undriven ports, unknown references

Timing Constraints (SDC)

Command	Example	Description
create_clock	create_clock -period 5 -name clk [get_ports clk]	Define clock — 5 ns period (200 MHz)
create_generated_clock	create_generated_clock -divide_by 2 -source clk [get_pins div_reg/Q]	Define divided/gated clock
set_clock_uncertainty	set_clock_uncertainty -setup 0.15 [all_clocks]	Add jitter/skew margin to setup analysis
set_clock_transition	set_clock_transition 0.08 [all_clocks]	Model clock edge slew rate
set_input_delay	set_input_delay -clock clk -max 1.5 [all_inputs]	Input arrival time (setup). Use -min for hold
set_output_delay	set_output_delay -clock clk -max 1.0 [all_outputs]	Output required time (setup). Use -min for hold
set_load	set_load 0.05 [all_outputs]	Set output load capacitance in pF
set_driving_cell	set_driving_cell -lib_cell BUFX4 [all_inputs]	Model input drive strength
set_max_fanout	set_max_fanout 20 [current_design]	Limit net fanout — triggers buffering
set_max_transition	set_max_transition 0.5 [current_design]	Max signal slew constraint (ns)
set_max_capacitance	set_max_capacitance 0.5 [current_design]	Max net capacitance constraint
set_dont_touch	set_dont_touch [get_cells u_clk_buf]	Preserve specific cell — no optimization allowed
set_dont_use	set_dont_use [get_lib_cells /SLOW]	Ban specific cells from synthesis mapping
set_false_path	set_false_path -from [get_ports async_rst]	Remove async reset / test path from timing analysis
set_multicycle_path	set_multicycle_path 2 -setup -to [get_cells u_slow*]	Allow path to take 2 clock cycles
set_case_analysis	set_case_analysis 0 [get_ports test_mode]	Fix signal value for timing analysis (e.g. test_mode=0 in normal)
read_sdc	read_sdc constraints.sdc	Load complete SDC file (preferred for complex designs)

Synthesis & Compilation

Command	Example	Description
compile	compile	Standard synthesis with basic optimization
compile -map_effort high	compile -map_effort high -area_effort medium	High-effort mapping with medium area focus
compile_ultra	compile_ultra	Aggressive optimization: retiming, datapath opt, better TNS
compile_ultra -no_autoungroup	compile_ultra -no_autoungroup	Preserve hierarchy — prevents automatic flattening
compile_ultra -gate_clock	compile_ultra -gate_clock	Enable automatic clock gating insertion
compile_ultra -retime	compile_ultra -retime	Enable register retiming for better timing
compile_ultra -area_high_effort_opto	compile_ultra -area_high_effort_opto	Aggressive area recovery after timing closure
compile -incremental_mapping	compile -incremental_mapping -only_design_rule	Incremental compile — only fix DRC violations
optimize_netlist -area	optimize_netlist -area	Post-compile area optimization without timing regression
ungroup	ungroup -all -flatten	Flatten hierarchy for cross-boundary optimization
group_path	group_path -name reg2out -from [all_registers] -to [all_outputs]	Group paths for targeted effort allocation

TCL — compile strategies

# Strategy 1: Safe — preserve hierarchy
compile_ultra -no_autoungroup

# Strategy 2: Aggressive timing closure
compile_ultra -retime -no_autoungroup
compile -incremental_mapping -only_design_rule

# Strategy 3: Area focused (after timing met)
compile_ultra -no_autoungroup -area_high_effort_opto
optimize_netlist -area

# Strategy 4: Fully flattened (small designs)
ungroup -all -flatten
compile_ultra

Reports & Analysis

Command	Example	Description
report_timing	report_timing -trans -nets -attr -nosplit	Critical path with transition times, net names, and attributes
report_timing -delay max	report_timing -delay max -nworst 10 -nosplit	Top 10 worst setup paths
report_timing -delay min	report_timing -delay min -nworst 5 -nosplit	Top 5 worst hold paths
report_timing -from -to	report_timing -from FF_A/Q -to FF_B/D -nosplit	Path between specific points
report_qor	report_qor > syn.qor	WNS, TNS, violating paths, area, levels — first check after compile
report_area	report_area -nosplit -hier > area.rpt	Hierarchical area breakdown in cell count and µm²
report_power	report_power -nosplit -hier > power.rpt	Dynamic + leakage power per module
report_cell	report_cell > cells.rpt	List all instantiated cells with reference library
report_net	report_net > nets.rpt	List all nets with driver/load information
report_constraint	report_constraint -all_violators	List all constraint violations (timing + DRC)
report_design_rules	report_design_rules -nosplit	Max fanout, max transition, max capacitance violations
report_clock	report_clock	All defined clocks, periods, and waveforms
report_path_group	report_path_group	List all path groups and their weights
all_violators	report_timing [all_violators]	Report timing on all violating endpoints

Netlist & Output

Command	Example	Description
write -format verilog	write -format verilog -hier -output netlist.v	Write hierarchical gate-level Verilog netlist
write -format ddc	write -format ddc -hier -output design.ddc	Save DDC checkpoint — opens in Design Vision
write_sdc	write_sdc -nosplit output.sdc	Write back-annotated SDC constraints
write_sdf	write_sdf -version 2.1 timing.sdf	Write Standard Delay Format for gate-level simulation
write_script	write_script -format tcl -output design.tcl	Write all applied constraints as a Tcl script
save_upf	save_upf design.upf	Save power intent (UPF) from the current design
write_test_model	write_test_model -output atpg.v	Write test model for Tetramax ATPG

Useful Object Queries

TCL — dc_shell queries

# Get all flip-flops
get_cells -hier -filter "is_sequential == true"

# Count total flip-flops
llength [get_cells -hier -filter "is_sequential == true"]

# Get all clock gating cells
get_cells -hier -filter "is_clock_gating_cell == true"

# Find all violating timing endpoints
report_timing -delay max [all_violators]

# Get all paths between two modules
report_timing -from [get_cells u_ctrl/*] \
              -to   [get_cells u_dp/*]

# Check for unclocked registers
foreach_in_collection reg [all_registers] {
  if { [get_attribute $reg clocks] == {} } {
    echo "Unclocked: [get_attribute $reg full_name]"
  }
}

# Report worst slack per path group
report_timing -group [get_path_groups]

Genus vs DC — Equivalent Commands

Both tools use industry-standard SDC constraints (create_clock, set_input_delay, etc.) — the constraint syntax is identical. The main differences are in library setup, synthesis execution, and reporting.

Operation	Cadence Genus	Synopsys DC
Set library path	set_db init_lib_search_path "/path"	set_app_var search_path "/path"
Set target library	set_db library {slow.lib}	set_app_var target_library "slow.db"
Read Verilog	read_hdl -language verilog top.v	analyze -format verilog top.v
Elaborate	elaborate top	elaborate top; link; uniquify
Check design	check_design -all	check_design
Load constraints	read_sdc constraints.sdc	read_sdc constraints.sdc
Generic synthesis	syn_generic	(part of compile)
Technology map	syn_map	(part of compile)
Full compile	synthesize -to_mapped -effort high	compile_ultra -no_autoungroup
Incremental opt	syn_opt -incr	compile -inc -only_design_rule
Set effort	set_db syn_global_effort high	compile_ultra (always high)
TNS optimization	set_db tns_opto true	set_cost_priority -delay (default)
Flatten hierarchy	ungroup -all -flatten	ungroup -all -flatten
Timing report	report_timing	report_timing -trans -nets -nosplit
QoR report	report_qor	report_qor
Area report	report_area -hier	report_area -nosplit -hier
Power report	report_power -hier	report_power -nosplit -hier
Write netlist	write_hdl > netlist.v	write -format verilog -hier -out netlist.v
Write SDC	write_sdc > out.sdc	write_sdc out.sdc
Write SDF	write_sdf > timing.sdf	write_sdf timing.sdf
Save checkpoint	write_db design.db	write -format ddc -hier -out design.ddc
Restore checkpoint	read_db design.db	read_ddc design.ddc
Don't touch	set_dont_touch [get_cells u_buf]	set_dont_touch [get_cells u_buf]
Don't use cells	set_dont_use [get_lib_cells /SLOW]	set_dont_use [get_lib_cells /SLOW]
False path	set_false_path -from [get_ports rst]	set_false_path -from [get_ports rst]
Multicycle path	set_multicycle_path 2 -setup -to ...	set_multicycle_path 2 -setup -to ...
Exit tool	exit	exit

Key Differences to Remember

Library format: Genus uses .lib files directly. DC requires .db (compiled binary) format — convert with lc_shell: read_lib + write_lib

Synthesis steps: Genus exposes three explicit steps (syn_generic / syn_map / syn_opt). DC bundles these inside compile/compile_ultra — you don't call them separately.

compile_ultra -no_autoungroup: Always use this flag unless you intentionally want DC to flatten your hierarchy. Without it, DC may silently ungroup modules and break downstream flows.

Genus set_db vs DC set_app_var: Genus uses set_db for most settings. DC uses set_app_var for application variables and set_attribute for design object attributes. They are not interchangeable.

SDC is identical: create_clock, set_input_delay, set_output_delay, set_false_path, set_multicycle_path — these are industry-standard SDC and work the same in both tools.

Incremental flow: After initial compile, use syn_opt -incr (Genus) or compile -inc (DC) for fast targeted fixes — much faster than re-running full synthesis.

Frequently Asked Questions

What is the difference between syn_generic, syn_map, and syn_opt in Genus?

syn_generic converts RTL to technology-independent Boolean logic (GTECH). syn_map maps that generic logic onto actual library cells from your technology. syn_opt does incremental post-map optimization — fixing timing, reducing area, improving TNS. You can run them in sequence or use synthesize -to_mapped to execute all three in one call.

What is the difference between compile and compile_ultra in DC?

compile performs standard synthesis. compile_ultra enables more aggressive algorithms: register retiming, advanced datapath optimization, and better TNS reduction. Always use compile_ultra -no_autoungroup to prevent DC from automatically flattening your hierarchy — without this flag, DC may silently destroy your module boundaries.

What does report_qor show and why is it important?

report_qor is the one-stop Quality of Results summary: Worst Negative Slack (WNS), Total Negative Slack (TNS), number of violating paths, total cell area, estimated wire length, and critical path logic levels. It's the first report you check after synthesis — WNS tells you the worst path, TNS tells you how much total work remains to close timing.

How do I write a gate-level netlist in Genus vs DC?

Genus: write_hdl > netlist.v. DC: write -format verilog -hierarchy -output netlist.v. Always export the SDC alongside it (write_sdc) so downstream STA (PrimeTime) and P&R (Innovus/ICC2) tools use the same timing intent.

What is the difference between set_dont_touch and set_dont_use?

set_dont_touch prevents the tool from modifying a specific cell instance or net already in the design — used for manually-placed clock buffers, test logic, etc. set_dont_use prevents the tool from picking certain library cell types when creating new logic — used to exclude cells with high leakage, cells not characterized for your corner, or cells incompatible with DFT rules.

Why does Genus need .lib files but DC needs .db files?

Genus can read Liberty (.lib) text format directly. Synopsys DC requires .db (Design Compiler binary database) format for faster loading. Convert .lib to .db using lc_shell: read_lib slow.lib; write_lib slow_lib -format db -output slow.db. Some foundry kits provide both formats; if only .lib is given, you need to compile it first.