Gating Clock Signals Across Domains
Clock gating (disabling a clock to save power) must be synchronized when the enable signal crosses clock domains:
// Gate enable comes from domain B, applies to domain A clock
sync_2ff gate_en_sync (.in(gate_en_b), .out(gate_en_sync_a), .clk(clk_a));
// Standard integrated gating cell with synchronized enable
wire gated_clk_a;
AOCLKBUF gate_cell (
.CK(clk_a),
.E(gate_en_sync_a), // Synchronized!
.Q(gated_clk_a)
);Key Takeaways
- ✅ Clock enable must synchronize before gating
- ✅ Use integrated gating cells (not manual gates)
Day 10: Multi-clock domain hierarchies.