3+ Clock Domains
Real chips have 5-10 clock domains (CPU, GPU, memory, I/O, sensors, etc.). How do you route signals safely between all pairs?
Clock Hierarchy Example:
• sys_clk (base, slowest)
• cpu_clk = 2× sys_clk
• mem_clk = 1.5× sys_clk
• i/o_clk = independent (from external PHY)
N domains = N(N-1)/2 CDC paths needed!
• sys_clk (base, slowest)
• cpu_clk = 2× sys_clk
• mem_clk = 1.5× sys_clk
• i/o_clk = independent (from external PHY)
N domains = N(N-1)/2 CDC paths needed!
Design Patterns
- Hub pattern: All signals route through one "common" slow domain
- Point-to-point: Direct CDC between each pair (complex)
- Related clock domains: PLL-derived clocks can share simpler synchronizers
Phase Alignment
If two clocks are phase-aligned (from same PLL), CDC is simpler but timing closure is tougher.
Day 11: Verification—testing CDC properly.