Testing Multi-Clock Designs
CDC verification needs independent clock generators for each domain:
module cdc_tb();
reg clk_a = 0, clk_b = 0, reset;
// Independent clocks (non-integer ratios stress CDC)
always #10 clk_a <= ~clk_a; // 50 MHz
always #15 clk_b <= ~clk_b; // 33.33 MHz
// Reset synchronized in each domain
initial begin
reset = 1;
#100 reset = 0;
end
// DUT
my_cdc_fifo dut (
.clk_a(clk_a), .clk_b(clk_b),
.reset(reset),
.wr_data(wr_data), .wr_en(wr_en),
.rd_data(rd_data), .rd_en(rd_en)
);
// Random stimulus across domains
initial begin
repeat(10000) begin
@(posedge clk_a) wr_en <= $random;
wr_data <= $random;
@(posedge clk_b) rd_en <= $random;
// Check rd_data consistency
end
end
endmoduleKey Testbench Techniques
- ✅ Use non-integer clock ratios (stress corner cases)
- ✅ Run 1M+ cycles to catch rare metastability events
- ✅ Random clock enables (skew, jitter)
- ✅ Monitor for data corruption and deadlock
Day 12: Formal CDC verification.