CXL 2.0 could pool memory — but each region still had one owner at a time. CXL 3.0 crosses the line that everything before it was building toward: true coherent sharing, where multiple hosts touch the same memory simultaneously. Combined with multi-level switching and a memory type that lives in the fabric itself, this is the version where CXL stops being an interconnect and becomes a genuine memory fabric.
This is the distinction the whole course has been pointing at. Recall from Day 7 that CXL 2.0 pooling assigns each memory segment to one host at a time — hosts take turns owning regions. CXL 3.0 adds memory sharing: multiple hosts coherently accessing the same memory segment at the same time, with hardware keeping every host's view consistent.
Sharing one region across multiple hosts sounds simple until you ask: when Host 1 modifies a cache line, how does Host 2 avoid reading a stale copy? The answer is the mechanism introduced on Day 5 — HDM-DB (Host-managed Device Memory with Back-invalidate) and its Back-Invalidate Snoop (BISnp).
This is exactly the hard case BISnp was built for: a memory device whose contents are cached by multiple agents, where any of them might write first. With BISnp, the memory device itself proactively manages cache states across all connected hosts — when a line changes, the device sends back-invalidates to wherever stale copies live, in any host. Without the device being able to snoop upstream like this, coherent multi-host sharing simply couldn't work; the old host-only snoop model of CXL 1.1 had no way to coordinate across independent hosts. BISnp is the enabling primitive under CXL 3.0's headline feature.
CXL 2.0's switching was capped at a single level and a directed tree topology (Day 7). CXL 3.0 breaks both limits with multi-level switching, enabling genuinely fabric-like structures:
The word "fabric" is now literal: CXL 3.0 systems can be wired into the same kinds of mesh and leaf-spine structures that data-center networks use, rather than the rigid single-switch tree of 2.0.
The most forward-looking addition is Global Fabric Attached Memory (GFAM). A Type 3 device in GFAM mode connects to a switch node without requiring a direct host connection — the memory lives in the fabric itself, reachable by any host through the switch, rather than hanging off one host's root port. Such a device is called a GFAM Device (GFD), and the scaling numbers are dramatic:
| Device Model | Nodes Supported |
|---|---|
| Multi-Logical Device (MLD) | Up to 32 nodes |
| GFAM Device (GFD) | Up to 4096 nodes |
Scaling figures per CXL 3.0 specification materials.
A single GFD can serve up to 4096 independent nodes simultaneously, for either pooled or shared memory — a 128× jump over the MLD's 32. This is the architectural foundation for rack-scale (and beyond) disaggregated memory: a pool of memory sitting in the fabric, addressable by thousands of nodes, decoupled entirely from any single host.
CXL 3.0's Back-Invalidate flow also unlocks direct peer-to-peer communication. A CXL or PCIe device can access another device's HDM-DB memory through CXL.io UIO (Unordered I/O) — without routing everything through the host. This is a big deal for accelerator-heavy systems: a GPU can reach another GPU's memory, or a shared memory pool, directly across the fabric, rather than bouncing every transfer off the CPU. It's the data path that makes accelerator-to-accelerator and accelerator-to-memory topologies efficient.
Unlike the 1.1→2.0 jump (which kept the same PHY), CXL 3.0 does advance the physical layer: it moves to the PCIe 6.0 PHY at 64 GT/s, doubling per-lane signaling. That jump also brings the larger 256-byte flit (up from the 68-byte flit of Days 2), which — as previewed — makes room for the forward error correction PCIe 6.0's PAM4 signaling requires. Day 10 covers that flit-format change in detail.
Why CXL 3.0 is the pivotal version: pooling (2.0) solved the allocation problem — no more stranded memory. Sharing (3.0) solves the collaboration problem — multiple hosts working on the same data in place, no copying. Together with multi-level fabrics and GFAM's 4096-node scaling, this is the version where "CXL memory fabric" stops being a marketing phrase and becomes an architecture you can actually build a disaggregated data center around.