CXL 3.0 made the fabric possible. The two versions after it make it practical at scale and secure enough to trust. Day 9 covers both: CXL 3.1's routing and security refinements that let fabrics actually grow large, and CXL 4.0's leap to the PCIe 7.0 physical layer — the newest generation, released just at the end of 2025.
CXL 3.1 (2023) didn't change the wire speed — it stayed on the same PCIe 6.0 PHY at 64 GT/s as 3.0. Instead, it refined the fabric with two headline additions that address the two things holding CXL 3.0 back from large real-world deployment: how far it can scale, and whether it can be trusted with sensitive data.
CXL 3.0 enabled non-tree topologies in principle, but its routing still had roots in the hierarchy-based (PCIe-tree-like) model. Port-Based Routing (PBR) replaces that: instead of routing by a rigid hierarchy, PBR routes by port, which is what actually enables much larger topologies and true any-to-any communication between nodes.
Why this matters: hierarchy-based routing scales the way a tree does — fine for modest sizes, but increasingly constraining as the fabric grows and you want arbitrary nodes to reach each other. PBR is the routing model that lets a CXL fabric span the kind of large, flexible, any-to-any topologies a rack-scale or multi-rack disaggregated-memory system actually needs. Note that PBR-capable switches were expected to arrive in 2026 or later — the spec preceded the silicon, as is common.
As CXL memory moves into shared, pooled, multi-tenant environments, a hard question arises: can a confidential workload trust memory that physically lives outside its own server? CXL TSP (Trusted-Execution-Environment Security Protocol) answers yes. It defines how to bring direct-attached CXL memory devices inside the trust boundary of a confidential VM (a TVM), so virtualization-based Trusted Execution Environments can host confidential computing workloads on CXL memory. TSP covers the full stack of what that requires:
Alongside PBR and TSP, CXL 3.1 also added memory-expander improvements including up to 32 bits of metadata and further RAS (reliability, availability, serviceability) enhancements — the unglamorous but essential robustness features large deployments demand.
CXL 4.0 Released in December 2025, CXL 4.0 is the newest generation — and unlike 3.1, it does advance the physical layer, moving to the PCIe 7.0 PHY at 128 GT/s. That's double the 64 GT/s of the CXL 3.x line, addressing data centers facing ever-heavier AI, HPC, and memory-intensive workloads.
| CXL 4.0 Feature | What It Delivers |
|---|---|
| PCIe 7.0 PHY, 128 GT/s | Double CXL 3.x bandwidth, with PCIe 7.0 FEC and CRC |
| Bundled Ports | Multiple physical ports operate as one logical entity — higher aggregate throughput without added latency |
| Native x2 Width | Adds x2 link width to increase fan-out across more devices |
| Up to 4 Retimers | Extends channel reach for large accelerators, multi-host fabrics, and pooling systems |
| Optical Support | Enables optical links for longer reach beyond copper limits |
| Latency-Optimized Flit | Supports both the standard 256B flit and an additional 256B latency-optimized flit |
CXL 4.0 details per the CXL Consortium 4.0 specification and December 2025 release materials.
Two of these deserve emphasis. Bundled ports gang multiple physical links into one logical pipe — the way you feed a bandwidth-hungry accelerator that a single link can't satisfy, without paying a latency penalty for the aggregation. And optical support is the quiet enabler of real disaggregation: copper links are distance-limited, but optical links can stretch memory pooling across longer reaches — the physical foundation for the multi-rack memory fabrics that pooling and sharing have been building toward since Day 7.
| Version | PCIe / Speed | Defining Addition |
|---|---|---|
| CXL 1.1 (2019) | 5.0 / 32 GT/s | Foundation: expansion, coherent devices |
| CXL 2.0 (2022) | 5.0 / 32 GT/s | Switch, pooling, hot-plug, IDE |
| CXL 3.0 (2023) | 6.0 / 64 GT/s | Sharing, multi-level fabric, GFAM |
| CXL 3.1 (2023) | 6.0 / 64 GT/s | PBR scale-out, TSP security |
| CXL 4.0 (Dec 2025) | 7.0 / 128 GT/s | Bandwidth doubling, bundled ports, optical |
The arc of the whole spec history in one line: 1.1 proved coherent memory over PCIe works; 2.0 made it poolable; 3.0 made it shareable and fabric-shaped; 3.1 made that fabric scale and made it secure; 4.0 doubled the bandwidth and added the optical reach to stretch it across racks. Each version removed the specific limit the previous one left behind — which is exactly why understanding them in order (Days 6–9) makes CXL feel like a clean progression rather than a pile of features.