Every day of this course so far has described what CXL is and how it's supposed to work. Day 14 asks a different question: who is actually building it, and what does the current industry structure tell us about where CXL's real value sits? The last twelve months have delivered one of the more surprising storylines in the whole CXL ecosystem — and it's not about a new spec feature, it's about who decided to stop making their own silicon.
You'd expect the three largest DRAM makers — Samsung, SK Hynix, and Micron — to be the natural leaders of CXL controller silicon, since they make the memory the controller sits in front of. Instead, all three have collectively halted in-house CXL controller commercialization. The reason isn't technical difficulty; it's a customer preference. Data center buyers strongly preferred flexible, modular architectures — a standalone CXL controller paired with ordinary commodity memory modules — over the expensive, vertically-integrated memory-plus-controller packages the memory giants had been building.
Micron's specific move makes the shift concrete: rather than continuing its own controller R&D, Micron adopted a CXL 3.0 controller from Primemas, a fabless semiconductor company that had been sampling that controller since mid-2025. This is a memory maker choosing to buy the controller layer from a specialist instead of building it in-house — the exact opposite of vertical integration.
Why this is a bigger deal than it sounds: DRAM makers vertically integrating controller logic was the default assumption for how CXL memory devices would be built. Customers rejecting that in favor of modular, commodity-memory-plus-standalone-controller designs is a real market signal about where CXL value actually concentrates — and it isn't in the memory chip itself.
With the memory giants stepping back, controller design leadership has shifted to specialized fabless companies — firms that design chips but don't operate their own fabs, instead having them manufactured by foundries like TSMC. Three names come up repeatedly in 2025–2026 industry coverage:
The Astera Labs / Microsoft Azure milestone is worth dwelling on, because it's the single clearest piece of evidence in this entire course that CXL memory has crossed from "specification and research demo" into "thing you can rent." A customer spinning up an Azure M-series VM in late 2025 could, for the first time at public hyperscale-cloud disclosure, be running on infrastructure with CXL-attached memory behind it — quietly, without needing to understand or operate any of the pool-appliance or Fabric Manager machinery from Day 11 themselves.
Controllers are only half the hardware story — Day 7's switch is the other half, and it has its own fast-moving vendor landscape. XConn Technologies built its reputation with a rapid one-two product cadence:
| Product | Date | Capability |
|---|---|---|
| Apollo | March 2024 | Industry's first CXL 2.0 / PCIe Gen 5 switch chip |
| Apollo 2 | March 2025 | Hybrid switch integrating both CXL 3.1 and PCIe Gen 6.2 on a single chip |
That track record made XConn an acquisition target rather than a long-term independent competitor: Marvell Technology acquired XConn for approximately $540 million. At OFC 2026 (March 17, 2026), Marvell announced two new 260-lane switches — one PCIe 6.0, one CXL 3.0 — both built directly on the acquired XConn intellectual property. Marvell has framed the combination of its own CXL memory-expansion controllers with the acquired XConn switch silicon as the industry's most comprehensive CXL portfolio for AI workloads, and industry analysis has explicitly described the deal as Marvell's two-pronged open-fabric play against NVLink — an attempt to make CXL-based scale-out infrastructure a credible, standards-based alternative to NVIDIA's proprietary interconnect for the parts of the system CXL is suited to (Day 12's memory expansion role, not GPU-to-GPU bandwidth).
Put the controller story and the switch story side by side, and a pattern emerges: CXL's ecosystem is consolidating around specialist silicon layers, not around vertically-integrated memory or system vendors. Memory makers supply commodity DRAM. Fabless companies (Astera Labs, Montage, Primemas) supply the controller logic that turns that DRAM into a CXL-addressable device. Switch specialists (XConn, now absorbed into Marvell) supply the fabric that connects controllers to hosts at scale. This is structurally much closer to how the ordinary DDR DIMM market has worked for decades — commodity memory chips, standard interfaces, competition concentrated in the interface/controller layer — than to a world where each memory vendor ships a proprietary, fully integrated CXL product.
Why this matters if you're evaluating CXL as a buyer or engineer: the "who do I trust for CXL hardware" question increasingly has a clean answer by layer — a fabless controller vendor for the memory-side silicon, a switch vendor (increasingly Marvell, post-XConn) for the fabric, and a commodity DRAM vendor for the memory itself. That's a healthier, more standard-market structure than betting on any single vertically-integrated vendor's roadmap, and it mirrors exactly the interoperability promise the CXL Consortium's open standard (Day 1) was designed to deliver in the first place.
This consolidation directly explains why Day 11's pooling deployment window (2026–2027) is realistic rather than aspirational: the controller supply chain no longer depends on three separate memory giants each shipping their own bespoke, unproven controller design. It depends on a smaller number of specialist vendors (Astera Labs, Montage, Primemas for controllers; Marvell/XConn for switches) iterating quickly on a narrower set of products — which is a faster, lower-risk path to mature, interoperable, second-sourceable CXL hardware than a fragmented vertically-integrated market would have been.