Fourteen days ago, this course opened with a memory wall and three sub-protocols. It closes here, with CXL sitting inside a genuinely crowded interconnect landscape — NVLink, UALink, Infinity Fabric — each solving a real problem, none of them replacing each other. Day 15 places CXL against its neighbors honestly, then looks at where the specification goes from CXL 4.0 onward.
The single most common misunderstanding about this landscape is treating it as one competition with a winner. It isn't. Each of these interconnects was built to solve a different problem, and the honest comparison is about fit, not a leaderboard:
| Interconnect | Primary Job | 2026 Status |
|---|---|---|
| CXL | CPU-centric memory expansion, pooling, tiering (scale-out) | Production: pooling deployments, cloud controller availability (Day 11, 14) |
| NVLink | Proprietary, extremely high-bandwidth GPU-to-GPU / CPU-to-GPU scale-up | Production: the only production-ready option for demanding AI training in 2026 |
| UALink | Open, multi-vendor alternative to NVLink for GPU-to-GPU scale-up | Early: UALink 1.0 spec released; hardware not expected until late 2026 at earliest |
| Infinity Fabric | AMD's own inter-die and GPU-to-GPU interconnect within its own accelerator platforms | Production: 4th-gen ships in AMD Instinct MI350X |
Status and specs per 2025-2026 industry coverage of each consortium/vendor's public roadmap and shipping products.
NVLink is the interconnect this course has referenced since Day 12's Grace Hopper discussion — and the numbers explain why nobody's proposing CXL replace it. NVLink 5.0 delivers roughly 100GB/s bidirectional per link, reaching 1.8TB/s per GPU, and a system like NVIDIA's GB200 NVL72 connects 72 Blackwell GPUs with 130TB/s of aggregate bandwidth. That is an entirely different order of magnitude from anything CXL's flit-based, CPU-centric links (Day 10) are built for.
But bandwidth isn't the only axis that matters. NVLink keeps the fabric proprietary and the system vertically integrated — it's NVIDIA's interconnect, for NVIDIA's GPUs. CXL, by contrast, is an open, multi-vendor standard (Day 1's founding premise), which is precisely why Day 14's ecosystem — Astera Labs, Montage, Primemas, Marvell/XConn — can exist as a competitive, interoperable supply chain in the first place. The trade is bandwidth-and-lock-in versus openness-and-a-different-job: NVLink moves unimaginable amounts of data between tightly-coupled GPUs; CXL extends how much memory those same systems, and ordinary CPU-only servers, can reach.
UALink (Ultra Accelerator Link), backed by AMD, Intel, and others, is frequently mentioned in the same breath as CXL — but it's actually aimed at NVLink's job, not CXL's. UALink 1.0 delivers 200GT/s per lane and supports up to 1,024 accelerators (versus NVLink's roughly 576-GPU maximum), explicitly positioning itself as an open, multi-vendor alternative to NVLink for GPU-to-GPU scale-up.
Why "CXL vs UALink" is the wrong framing: UALink solves GPU-to-GPU bandwidth at scale. CXL solves memory expansion, pooling, and tiering. A system can — and likely will — use both: UALink (or NVLink) connecting GPUs to each other at massive bandwidth, and CXL separately connecting hosts and accelerators to expanded, pooled, or tiered memory. They stack rather than compete, exactly like Day 12's Grace Hopper example showed NVLink-C2C and CXL doing inside one chip.
Timeline-wise, UALink is meaningfully behind CXL's production maturity: UALink hardware isn't expected until late 2026 at the earliest, with real deployments likely extending into 2027 — a full generation behind CXL's already-shipping pooling deployments and cloud controller availability from Days 11 and 14. That gap exists for a structural reason, not because UALink's backers are behind schedule: GPU-to-GPU scale-up fabrics at 1,024-accelerator scale are a harder coordination problem than CXL's memory-expansion use case, mirroring exactly the "pooling ships before sharing" pattern from Day 11.
AMD's Infinity Fabric is a third point of comparison, but it's arguably the least direct competitor of all. The 4th-generation Infinity Fabric in AMD's Instinct MI350X platform delivers 5.5TB/s of inter-die interconnect and 1,075GB/s of aggregate GPU-to-GPU bandwidth across eight fully-connected GPU OAM modules — but this is AMD's own internal fabric for its own accelerator platform, comparable in scope to NVLink rather than to CXL's open, cross-vendor memory role. It's evidence that every major accelerator vendor has independently converged on needing a very-high-bandwidth proprietary fabric for tightly-coupled GPU clusters, while still leaving room for CXL to handle the separate memory-expansion problem at the CPU/host level.
CXL 4.0, covered on Day 9, was released in November 2025: it doubled bandwidth to 128GT/s via the PCIe 7.0 physical layer and introduced bundled ports enabling connections up to 1.5TB/s, plus the multi-rack memory pooling scale this course has tracked since Day 11. If the pattern from Days 6–10 holds — and it has held for every version jump this course has covered — future CXL development will keep extending the existing primitives (sub-protocols, device types, the flit format, ARB/MUX, Fabric Manager) rather than replacing them: larger and more flexible fabrics, more bandwidth, and eventually mature multi-host coherent sharing (Day 8's CXL 3.0 capability) operating at the scale that pooling operates at today.
The most interesting open question: proposals like Huawei's UB-Mesh (presented at Hot Chips 2025) imagine unifying PCIe, NVLink-class fabrics, and even TCP/IP-style networking into one mesh supporting extremely high per-chip bandwidth. These remain nascent research proposals, not shipping standards — but they're a signal that the industry hasn't settled on today's specialized-interconnect landscape as a permanent end state. Whether CXL's open-standard model expands to absorb more of that unification, or stays focused on its current memory-centric lane while NVLink/UALink-class fabrics handle scale-up, is the genuinely unresolved question this course leaves you with.
CXL exists because memory stopped scaling as fast as compute (Day 1), and it solves that with three sub-protocols (Day 3) serving three device types (Day 4), coordinated through bias modes and coherence models (Day 5) that grew from simple direct-attach (Day 6) into switched pooling (Day 7), true multi-host sharing (Day 8), routable and secured fabrics (Day 9), all riding on a flit format built to survive PAM4's error rates (Day 10). That architecture is now solving a real, dollar-denominated problem — stranded memory (Day 11) and the AI memory wall (Day 12) — through a concrete Linux software stack (Day 13) built by a consolidating, increasingly specialized industry (Day 14), sitting alongside — not replacing — NVLink, UALink, and Infinity Fabric in the wider interconnect landscape you just read about.
Fifteen days, from "what even is CXL" to the real silicon shipping in 2026. If this helped, share it with someone wrestling with the same memory wall — and go build something with what you now understand.