DFT Challenges at Advanced Nodes (3nm, 2nm)
Every new technology node tightens the tolerances that define a working transistor. At 3nm and 2nm, the gap between a perfectly formed device and a defective one can be a single misplaced atom. This creates a new category of DFT problems that did not exist at 28nm or even 7nm.
At planar CMOS nodes, the dominant defect mechanisms were relatively simple: missing contacts, metal shorts, bridging faults between adjacent wires. Standard stuck-at ATPG was well-suited to detecting these. But at FinFET (7nm–3nm) and Gate-All-Around (GAA, 2nm and below) nodes, three new classes of defects become significant:
FinFET and GAA Transistor Defects
A FinFET transistor controls current through a thin vertical silicon fin. The gate wraps around three sides of the fin. If the fin is broken, slightly too wide, or has a crystal defect, the transistor behaves abnormally — but may not present as a clean stuck-at fault. A broken fin can manifest as a high-resistance path, which causes a transition fault (signal switches too slowly) rather than a stuck-at fault. GAA (nanosheet) transistors, used at 2nm, have even tighter nanosheet stacks where sheet-to-sheet bridging or sheet undercut defects create complex multi-terminal fault behaviors that purely logic-level models miss.
Back-End-of-Line (BEOL) Via Defects
At advanced nodes, metal pitches are so tight that via formation becomes one of the leading yield limiters. A missing via (open) creates a high-resistance path that may allow DC continuity (fooling a stuck-at test) but causes timing failures at speed. Partially formed vias — common in narrow single-via connections — increase resistance and cause intermittent failures that are temperature-dependent. This is why at-speed testing (transition fault + path delay) is mandatory at advanced nodes, not optional.
EUV Lithography Stochastic Defects
Extreme ultraviolet (EUV) lithography uses 13.5 nm wavelength light to print features below 30nm. At such small dimensions, photon statistics create stochastic (random) variation: the number of photons hitting a given feature varies shot-to-shot. This causes probabilistic bridging between adjacent features, line-edge roughness, and random pattern dependent open/short defects. These defects are distributed randomly across the wafer and are not correlated with design structure — meaning systematic ATPG patterns alone cannot guarantee detection. High-volume manufacturing (HVM) test must use sufficiently diverse pattern sets to statistically capture stochastic defects.
A stuck-at fault model assumes a net is permanently '0' or '1'. But at 3nm/2nm, many real defects cause the net to be slow (a transition fault), or to fail only at certain voltage/temperature corners (a parametric fault), or to have a defect inside a standard cell that doesn't affect any net between cells. None of these are caught by stuck-at ATPG alone.
Cell-Aware ATPG
Traditional ATPG treats each standard cell as an ideal logic function: a NAND2 is modeled as output = NOT(A AND B). It knows nothing about the transistors inside the cell. Cell-aware ATPG breaks this abstraction barrier by incorporating transistor-level defect models directly into the ATPG engine.
How Cell-Aware ATPG Works
The foundry — or the EDA tool using foundry-provided data — characterizes every standard cell in the library by running transistor-level simulation with injected defect models (bridging between specific internal nodes, open connections on internal metal segments, etc.). The result is a cell defect table: for each cell type, a list of intra-cell defects and the input pattern required to detect each one. This table is provided to the ATPG tool (e.g., Siemens Tessent CellModelGen).
During ATPG, in addition to targeting stuck-at and transition faults on the nets connecting cells, the tool also targets each entry in the cell defect tables. The result is a superset of traditional ATPG patterns that also cover internal cell defects.
What Intra-Cell Defects Look Like
Consider a 2-input NAND cell built from 4 transistors (2 PMOS in parallel, 2 NMOS in series). A bridging defect between the internal node connecting the two NMOS transistors and the output node will not manifest as a stuck-at fault on any external net. It will only be detectable with a specific combination of A and B inputs that creates a current path between those internal nodes. Logic-level ATPG cannot find this pattern because it has no knowledge of the internal topology. Cell-aware ATPG does.
| ATPG Type | Fault Model | What It Catches | Typical Coverage |
|---|---|---|---|
| Stuck-At ATPG | SA0, SA1 on nets | Stuck nodes, major opens/shorts | ~98–99% |
| Transition Fault ATPG | Slow-to-rise, slow-to-fall | High-resistance paths, slow vias | ~92–96% |
| Cell-Aware ATPG | Intra-cell bridging/opens | Internal cell defects | +1–3% incremental |
| Path Delay ATPG | Path delay violations | Cumulative slow paths | Critical paths only |
The incremental 1–3% coverage from cell-aware ATPG may sound small, but at the DPPM (defects per million) level required for automotive or high-reliability silicon, it translates to dozens fewer escaped defects per million units — which is significant at high production volumes.
Chiplet Architecture and DFT Challenges
Moore's Law scaling has become increasingly difficult and expensive. The industry's response is chiplet-based design: instead of integrating everything onto one large monolithic die (which has poor yield as die area grows), functions are split across multiple smaller dies — chiplets — assembled together on an advanced package or interposer.
A modern chiplet system-in-package (SiP) might contain:
- A compute die (CPU/GPU cores) at the latest node (3nm)
- HBM memory stacks attached to the same package
- An I/O die at a mature node (7nm or 12nm) for high-speed PHYs
- A passive or active interposer routing signals between dies
Each of these brings new DFT challenges that simply do not exist for a monolithic SoC:
Micro-bumps, C4 bumps, hybrid bonds, and TSVs between chiplets can all fail (open, short, leakage). These interconnects are not part of any die's scan chain and require dedicated test strategies.
Once assembled into a package, an ATE probe cannot directly contact die-level pads. Test must reach each die through the package I/O — requiring a standardized access mechanism per die.
Different chiplets may come from different vendors with different DFT implementations. A standard interface is required for test interoperability between chiplets.
Assembling a defective die wastes expensive packaging. Every die must be tested individually (pre-bond, on-wafer) before assembly — which requires test access to a die before its package pins exist.
IEEE P1838 — 3D Test Access Standard
IEEE P1838 (now ratified as IEEE Std 1838-2019) is the standard for test access in 3D stacked die packages. It extends the JTAG concept (IEEE 1149.1) to multi-die assemblies where traditional JTAG is insufficient.
The Core Problem P1838 Solves
IEEE 1149.1 assumes all test access pins (TDI, TDO, TMS, TCK, TRST) exist at the package boundary and connect through a single TDR (test data register) chain. In a 3D stack, Die A sits on top of Die B, which sits on the package substrate. Die A's logic is accessible only through Die B's die-to-die interface — there are no dedicated test pads on Die A's external surface. P1838 defines how to build a test access path that traverses Die B to reach Die A.
P1838 Die Wrapper
Each die in a P1838-compliant stack is surrounded by a die wrapper: a ring of standardized boundary cells at every die-to-die interface port. These wrapper cells function similarly to IEEE 1149.1 boundary scan cells but are designed for die-to-die signals rather than package I/O. The wrapper allows:
- Isolation test: Force/observe values at the die boundary, isolating the die from its neighbors
- Interconnect test: Drive patterns through the wrapper into the die-to-die interconnect and observe results at the receiving die's wrapper
- Internal test: Pass test data through the die's internal scan chains while the wrapper holds the die boundary stable
P1838 Test Modes
| Test Mode | What Is Tested | Die Wrapper State |
|---|---|---|
| Die Internal Test | Logic/memory inside one die | Wrapper holds boundary inputs stable; die's scan chains are active |
| Interconnect Test | TSVs / micro-bumps between dies | Upper die wrapper drives; lower die wrapper observes (or vice versa) |
| System Test | Full stack in functional mode | All wrappers in bypass/transparent mode |
KGD — Known Good Die
Known Good Die (KGD) testing is the strategy of fully testing each chiplet before packaging it with other chiplets. This is economically critical because advanced packaging (CoWoS, EMIB, SoIC) is extremely expensive — far more expensive than the cost of testing an individual bare die.
The Yield Math
Suppose you have three chiplets assembled into one package, each with 95% yield. The package yield if no pre-assembly test is done is approximately 0.95 × 0.95 × 0.95 = 85.7%. After spending packaging cost on every assembled unit, 14.3% must be discarded. If KGD testing first culls defective dies (increasing effective input yield to ~99% per die), assembled yield rises to 0.99³ = 97%. The cost savings from avoiding wasted packaging on defective assemblies typically justify the cost of pre-assembly wafer-level test by a large margin.
Pre-Bond Test
Pre-bond test happens while dies are still on the wafer, before dicing and stacking. Temporary test pads or probe-accessible pads are included in the die design specifically for this purpose. The DFT team must plan these pads early in the design — they consume area and must be placed at probe-accessible locations. The ATE contacts these pads directly with a wafer probe card and runs the full ATPG pattern set.
Post-Bond Test
After stacking (but before final packaging), post-bond test uses the IEEE P1838 wrappers to test the assembled dies and their interconnects. This catches defects introduced by the assembly process itself (TSV cracking under bonding pressure, micro-bump misalignment, etc.).
1. Wafer-Level Test (pre-dice): Full ATPG + BIST via temporary probe pads. Yield-maps dies.
2. Pre-Bond Die Test (optional, after dice): Burn-in or additional test for high-reliability applications.
3. Post-Bond Stack Test (P1838): Interconnect continuity + die-internal test through TSV path.
4. Package-Level Test: Final functional test through package BGA pins.
UCIe — Universal Chiplet Interconnect Express Test
UCIe (Universal Chiplet Interconnect Express) is an industry standard (backed by Intel, AMD, Arm, TSMC, Samsung, and others) that defines the physical layer, link layer, and protocol adapter for die-to-die interconnects. It enables chiplets from different vendors to interoperate on the same package.
UCIe defines three dedicated test modes for verifying the die-to-die link:
1. Loopback Mode
The transmitter (TX) of the UCIe PHY on Die A is connected back to the receiver (RX) within the same UCIe PHY — without the signal leaving Die A. This tests the TX-to-RX signal path entirely within one die. It verifies the PHY circuitry functions correctly and establishes a baseline before testing the actual inter-die link.
2. Pattern Mode (Link Test)
Each UCIe PHY has a built-in pattern generator that can drive known sequences (PRBS-7, PRBS-31, clock patterns) onto the high-speed lanes. The receiving PHY on the adjacent die has a pattern checker that verifies the received data. This tests the actual bump/interconnect between dies: signal integrity, skew, jitter, and eye margin. Link margin testing uses this mode to characterize the die-to-die channel.
3. Sideband Test Mode
UCIe includes a low-speed sideband channel (SB) separate from the high-speed data lanes. The sideband channel carries initialization, configuration, and test commands using a simple two-wire protocol. During test, the sideband channel can be used to send test commands to a UCIe PHY even when the high-speed lanes are not yet operational — enabling test sequencing and fault diagnosis without requiring the main data path to be functional first.
| UCIe Test Mode | What Is Verified | When Used |
|---|---|---|
| Loopback | PHY TX/RX within one die | Pre-assembly wafer-level test |
| Pattern (PRBS) | Die-to-die bump + signal integrity | Post-assembly package test |
| Sideband | Control path, test command delivery | During all test phases |
| Protocol-Level | UCIe link protocol handshake | System-level bring-up |
IJTAG — IEEE 1687 Instrument Networks
IEEE 1687, commonly called IJTAG (Internal JTAG), is a significant evolution of the IEEE 1149.1 JTAG standard. While JTAG defines a fixed serial scan chain, IJTAG defines a reconfigurable network of on-chip test instruments.
The Problem IJTAG Solves
Modern SoCs contain dozens of on-chip test instruments: BIST controllers, thermal sensors, analog monitors, PLL characterization modules, embedded logic analyzers, memory repair controllers. In a traditional JTAG approach, all of these would be connected in a fixed chain. Accessing the BIST controller for one memory block would require shifting through all other instruments — potentially millions of clock cycles of overhead. IJTAG solves this with SIB (Segment Insertion Bit) cells.
SIB Cells
A SIB cell is a special 1-bit scan element that controls whether a downstream instrument segment is included in or bypassed from the active scan path. When SIB = 0, the downstream segment is bypassed (skipped). When SIB = 1, the downstream instrument segment is inserted into the active chain. By selectively opening SIBs, the scan path is dynamically reconfigured to include only the specific instruments needed for a given test operation.
ICL and PDL: The IJTAG Languages
IJTAG defines two companion languages:
- ICL (Instrument Connectivity Language): Describes the structural topology of the instrument network — which SIBs exist, which instruments are connected to which SIBs, and the signal names for each. ICL is analogous to a structural netlist for the test network.
- PDL (Procedural Description Language): Describes the procedures for using each instrument — how to load a test command, how to read a result, what sequence of SIB operations to perform to access a specific sensor. PDL is analogous to a test program that drives the instrument network.
EDA tools (Siemens Tessent, Synopsys DFTMAX) can read ICL/PDL to automatically generate test patterns and ATE programs for the instrument network.
Die-to-Die Interconnect Testing
After understanding the standards, let's focus on the practical challenge: how do we actually test the physical interconnects between dies?
Interposer interconnects and TSV micro-bumps can fail in several ways:
- Open: The bump is missing or broken — no electrical continuity. Detected by: driving a logic '1', failing to observe it at the receiver.
- Short: Two adjacent bumps are electrically connected. Detected by: driving opposite values (0/1) on adjacent signals and observing bridging.
- High resistance: The bump has higher than expected resistance, causing signal integrity degradation at speed. Detected by: at-speed pattern test or loopback BER testing.
- Capacitive leakage: Leakage between a bump and an adjacent structure. Detected by: DC parametric test or leakage current measurement.
Interconnect Test Approach 1: Boundary Scan
If both dies implement IEEE P1838 wrappers, the wrapper cells on Die A's bottom interface drive known values, and the wrapper cells on Die B's top interface observe them. This is essentially boundary scan applied to the die-to-die interface — testing each signal for stuck-at and bridging faults.
Interconnect Test Approach 2: UCIe PRBS Loopback
For high-speed differential lanes (the main UCIe data path), DC boundary scan is insufficient — the lanes operate at multi-Gbps speeds where analog signal quality matters. UCIe PRBS pattern mode drives and receives high-speed patterns to verify bit error rate (BER) is within specification across the interconnect.
Interconnect Test Approach 3: Dedicated Die-to-Die BIST
Some designs include a dedicated die-to-die link BIST engine — a built-in circuit that independently exercises the die-to-die lanes with programmable patterns and counts errors. This BIST can run autonomously in the background during system bring-up or as part of a production test program.
Advanced Packaging: CoWoS and SoIC
Two advanced packaging technologies from TSMC are now widely deployed and introduce unique DFT considerations:
CoWoS (Chip-on-Wafer-on-Substrate)
CoWoS places chiplets on a large silicon interposer (the "Wafer" layer) before mounting the interposer on the package substrate. The silicon interposer provides extremely dense routing between chiplets. Interconnects between chiplets and the interposer use controlled-collapse chip connection (C4) micro-bumps at pitches of 40–55 μm. DFT implication: micro-bump opens and shorts can be tested with P1838 wrappers driving across the interposer. The interposer itself (being a passive silicon die) may contain test structures for its routing layers.
SoIC (System on Integrated Chip) — Hybrid Bonding
SoIC takes chiplet integration to the extreme: dies are bonded face-to-face using Cu-Cu hybrid bonding at sub-micron pitch (less than 1 μm between bond pads). This achieves extremely high bandwidth density between stacked dies — far beyond what micro-bumps can offer. The DFT challenge: at sub-micron pitch, no physical probe can contact individual bond pads. The only way to test Cu-Cu bonds is through built-in test structures — either dedicated BIST engines or specialized continuity test modes designed into the interface. This makes comprehensive DFT planning at RTL stage mandatory, not optional, for SoIC designs.
Interview FAQ — Day 11
What is IEEE P1838 and why is it needed for 3D ICs?
IEEE P1838 (IEEE Std 1838-2019) is the standard for test access in 3D stacked die packages. Traditional JTAG (IEEE 1149.1) assumes all test signals (TDI/TDO/TMS/TCK) arrive at the package boundary and connect to a single planar die. In a 3D stack, dies are stacked vertically — an ATE cannot directly probe the die in the middle of a stack.
P1838 solves this by defining: (1) a standardized die wrapper (boundary cells at every die-to-die interface), (2) a test data path that traverses from the substrate upward through each die, and (3) test modes for isolating each die, testing die-to-die interconnects, and testing each die's internal logic independently. It extends JTAG's concepts to 3D by standardizing how test flows through the stack.
What is KGD testing and why is it important for chiplet yield?
KGD (Known Good Die) testing means fully testing each die while it is still a bare die (on-wafer) before it is assembled into a multi-chiplet package. Advanced packaging is expensive — if a defective die is assembled, the entire package including all other dies must be discarded.
By multiplying individual die yields: if three 95%-yield dies are assembled without pre-test, package yield = 0.95³ = 85.7%. With KGD screening elevating effective yield to 99%, package yield becomes 0.99³ = 97%. The savings from avoiding wasted packaging cost on defective assemblies typically pays for the additional wafer-level test cost many times over.
How does IJTAG (IEEE 1687) differ from JTAG (IEEE 1149.1)?
JTAG (IEEE 1149.1) defines a fixed-topology serial scan chain. All instruments are wired in a fixed order. Accessing any instrument requires shifting through the entire chain — which can mean millions of clock cycles of overhead in a complex SoC.
IJTAG (IEEE 1687) replaces the fixed chain with a reconfigurable network using SIB (Segment Insertion Bit) cells. Each SIB can insert or bypass a downstream instrument segment. By selectively opening only the SIBs on the path to the target instrument, the active scan path includes only the instrument of interest — dramatically reducing access overhead. IJTAG also defines two languages (ICL for structure, PDL for procedures) that allow EDA tools to automatically generate test programs for complex instrument networks.
What DFT challenges does a chiplet architecture introduce vs a monolithic SoC?
A monolithic SoC has all logic on one die with a single set of test I/O pins and a single JTAG TAP. Every internal node can in principle be reached by the on-chip scan chain. Chiplets introduce four new categories of challenge:
1. Die-to-die interconnects: Micro-bumps, TSVs, and hybrid bonds must be separately tested — they are not part of any die's internal scan chain.
2. Test access after packaging: No direct probe access to die-level signals exists after packaging. A standardized access mechanism (P1838 wrappers, IJTAG, UCIe sideband) is mandatory.
3. Multi-vendor interoperability: Chiplets from different vendors may use different DFT implementations — the test interface must be standardized.
4. Known Good Die: Each chiplet must be pre-tested before assembly to avoid costly packaging waste — requiring wafer-level test infrastructure specifically designed for pre-bond testing.
What is cell-aware ATPG and how does it improve coverage at advanced nodes?
Traditional ATPG models each standard cell as an ideal logic function (NAND, NOR, FF, etc.) and generates patterns for stuck-at or transition faults on the nets connecting cells. It has no knowledge of what is inside each cell.
Cell-aware ATPG incorporates foundry-provided cell defect tables that list intra-cell defects: bridging between internal transistor nodes, missing contacts inside a cell, opens on internal metal connections. These defects cannot be detected by logic-level patterns because they do not affect any inter-cell net in a clean stuck-at fashion — only specific input combinations expose them by creating current paths between internal nodes.
At 5nm and below, intra-cell defects become a significant fraction of all manufacturing defects. Cell-aware ATPG adds 1-3% incremental defect coverage on top of traditional ATPG — which at automotive DPPM targets means significantly fewer escaped defects per million units.
What are the test modes in UCIe and what does each verify?
UCIe (Universal Chiplet Interconnect Express) defines three main test modes for the die-to-die link:
Loopback mode: The UCIe PHY's transmitter is looped back to its own receiver within the same chiplet. Tests the PHY circuitry's TX and RX without using the actual inter-die link. Used during pre-assembly wafer-level test.
Pattern mode (PRBS): The PHY drives known pseudo-random bit sequences onto the high-speed lanes and the receiving PHY checks them. Tests the actual die-to-die interconnect (micro-bumps, signal integrity, eye margin) at full link speed. Used after assembly to characterize link health.
Sideband test mode: Test commands travel over the low-speed sideband channel independent of the high-speed data lanes. This allows test initialization and configuration to occur even when the main data path is not yet operational — critical for test bring-up sequencing.