End-to-End DFT Flow + 30 Interview Questions

The Complete End-to-End DFT Flow

A production DFT flow has 17 distinct steps. Each step builds on the previous — skipping one causes failures downstream. Here is the complete flow from RTL to ATE production test.

DFT Constraints File — Reference

The DFT constraints file defines all test signals and scan configuration. Here is a realistic example covering the most common directives:

# ── DFT Signal Definitions ─────────────────────────────────
# Test mode pin — when high, enables scan operation
set_dft_signal -view existing_dft -type TestMode \
               -port [get_ports test_mode]

# Scan enable — shifts scan chains when high
set_dft_signal -view existing_dft -type ScanEnable \
               -port [get_ports scan_en] -active_state 1

# Scan clock — used during shift mode
set_dft_signal -view existing_dft -type ScanClock \
               -port [get_ports clk] -timing {45 55}

# Functional clock — used for capture (at-speed)
set_dft_signal -view existing_dft -type MasterClock \
               -port [get_ports clk] -timing {45 55}

# Reset — must be inactive during scan
set_dft_signal -view existing_dft -type Reset \
               -port [get_ports rst_n] -active_state 0

# ── Scan Chain Configuration ─────────────────────────────────
set_scan_configuration -chain_count 32 \
                       -max_length 512  \
                       -style multiplexed_flip_flop

# ── EDT Compression ──────────────────────────────────────────
set_dft_signal -view spec -type Edt_clock \
               -port [get_ports edt_clk]
set_compression_options -external_channel_count 16 \
                        -interface_type edt

# ── Transition Fault Setup ───────────────────────────────────
set_dft_signal -view existing_dft -type CaptureEnable \
               -port [get_ports capture_en]

# ── Clock Gating Bypass ──────────────────────────────────────
# Force all clock gates transparent during scan shift
set_dft_signal -view existing_dft -type CG_Enable \
               -port [get_ports cg_test_en] -active_state 1

DFT Sign-off Checklist

Every item below must be green before the DFT lead signs off and the design proceeds to tape-out. A single red item is a tape-out blocker.

30 DFT Interview Questions — Expert Answers

Organized into 6 categories. These are the questions actually asked at Qualcomm, Intel, NVIDIA, Samsung, Arm, and DFT EDA companies (Siemens, Synopsys, Cadence).

Category A — Fault Models & Coverage

Category B — Scan Design

Category C — ATPG Algorithms

Category D — BIST (LBIST & MBIST)

Category E — JTAG & Advanced DFT

Category F — Power, Sign-off & Career

DFT Tools Reference

DFT Career Paths

Companies hiring DFT engineers: Qualcomm (mobile SoC DFT), Intel (server/AI DFT), NVIDIA (GPU/AI DFT), Apple (custom silicon DFT), Samsung Semiconductor (memory + logic DFT), Arm (IP-level DFT methodology), Siemens EDA / Synopsys / Cadence (tool development and applications engineering).

What to Do Next

• Practice ATPG: Download a free Verilog netlist (e.g., ISCAS-85 benchmark circuits) and run ATPG using open-source tools or academic licenses of Tessent/TetraMAX.
• Study RTL: The RISC-V from Scratch course teaches RTL design — understanding the design you're testing makes you a better DFT engineer.
• Physical Design: The Physical Design course covers floorplan, placement, routing — DFT engineers need to understand routing congestion impact of long scan chains.
• Read JEDEC / IEEE standards: IEEE 1149.1 (JTAG), IEEE 1687 (IJTAG), IEEE P1838 (3D test). Even skimming the scope and definitions sections builds real expertise.
• Job prep: Use the 30 Q&A from this page as flashcards. The DFT interview at most companies is 2-3 rounds: (1) fault models and scan basics, (2) ATPG and BIST deep-dive, (3) system-level DFT and past project discussion.