MBIST vs ATPG
People search “MBIST vs ATPG” because both say pass or fail, and they are not the same test. MBIST asks whether a memory stored the bits. ATPG asks whether the logic answered like a good chip. This page starts with a 4-word, 8-bit RAM you can count, then adds the fault types and the March test interviewers expect.
Difference between MBIST and ATPG in one minute
| MBIST | ATPG | |
|---|---|---|
| Full name | Memory Built-In Self-Test | Automatic Test Pattern Generation |
| Tests | SRAM, ROM, register files | Gates and scan flip-flops |
| Pattern lives | Inside the chip, generated while the test runs | On the tester, shifted in through scan |
| Sentence | Write it, read it, compare it | Apply it, capture it, compare it |
1. Start with an 8-bit RAM
This example RAM has 4 addresses. Each address stores 8 bits. That is 4 × 8 = 32 storage bits. Real chips have millions of bits. The idea does not change.
| Address | Stored data | Width |
|---|---|---|
| 0 | 8 bits | one word |
| 1 | 8 bits | one word |
| 2 | 8 bits | one word |
| 3 | 8 bits | one word |
Normal RAM pins
- Address — which word you want (0, 1, 2, or 3).
- Write enable — 1 means “store this,” 0 means “just read.”
- Write data — the 8 bits going in.
- Read data — the 8 bits coming out.
- Clock — the drumbeat. The write or read happens on a clock edge.
2. Memory fault models (what MBIST is hunting)
A stuck cell is the easiest picture. Real SRAM tests also look for neighbors that disturb each other and for a decoder that opens the wrong word.
| Fault | Plain meaning | How a test sees it |
|---|---|---|
| Stuck-at (SAF) | The cell is frozen at 0 or frozen at 1. | Write the opposite value, read it back, it did not change. |
| Transition (TF) | The cell is slow. It will flip, but not in time. | Write 0, then write 1, then read immediately. A slow cell still shows 0. |
| Coupling (CF) | Writing one cell flips a neighbor. | March up and down the addresses so a write is followed by a read of the victim. |
| Address decoder (AF) | Address 2 opens the wrong word, or two addresses share one cell. | Unique data per address. If two reads return the same word, the decoder is lying. |
Neighborhood pattern-sensitive faults (NPSF) go further: the center cell depends on the pattern in the cells around it. Production MBIST usually starts with March algorithms, not with a full NPSF suite, because March covers the faults that actually escape to customers at a practical test time.
A factory defect can freeze one tiny cell. The rest of the RAM still looks fine.
Stuck-at-0 on bit 3 of address 2
We write 11111111. Bit 3 cannot become 1. It stays 0. Counting from the right, bit 0 is the last digit.
Expected ≠ read → fault detected. That one mismatch is the whole point of the test.
3. How MBIST works
MBIST means Memory Built-In Self-Test. A small controller sits next to the RAM. It writes patterns, reads them back, and compares. The outside tester does not have to invent every address.
Inside that controller you usually find:
- an address counter (0, then 1, then 2, then 3)
- a pattern generator (all zeros, all ones, or a march pattern)
- a comparator
- a small state machine that orders the steps
- a pass/fail bit
A first sequence (not the full March algorithm)
Store 00000000 at every address.
Read every address. Each word must be 00000000.
Store 11111111 at every address.
Read every address. Each word must be 11111111.
Real MBIST uses longer marches (March C− and friends) so a cell is checked after its neighbors change. This four-step walk is enough to see a stuck-at-0 cell.
// Simplified MBIST idea — one address shown
WRITE_0:
write_enable = 1;
write_data = 8'b00000000;
address = addr;
READ_0:
write_enable = 0;
expected_data = 8'b00000000;
if (read_data != expected_data) fail = 1;
WRITE_1:
write_enable = 1;
write_data = 8'b11111111;
READ_1:
write_enable = 0;
expected_data = 8'b11111111;
if (read_data != expected_data) fail = 1;
Try it
| Address | Stored bits | Check |
|---|
3.8 What is a March algorithm?
A March test does not jump around the RAM at random. It marches from the lowest address to the highest, or back down, and at every stop it does the same short list of reads and writes.
The four buttons above are a teaching march: write all zeros, read them, write all ones, read them. That catches a cell stuck at 0 or stuck at 1. It misses many coupling faults, because it never reads a neighbor after a write.
March C− is the algorithm you will hear in DFT interviews. In shorthand, each arrow is one pass over every address. The letters inside are the operations at that address, in order. w0 means write 0. r1 means read and expect 1.
March C− (van de Goor) ↕ (w0) ↑ (r0, w1) ↑ (r1, w0) ↓ (r0, w1) ↓ (r1, w0) ↕ (r0) ↑ = low address to high ↓ = high address to low ↕ = either direction
On our 4-word RAM, the second element ↑ (r0, w1) means: at address 0, read and expect 0, then write 1. Then the same pair at address 1, then 2, then 3. The down-arrows repeat the idea from address 3 back to 0, which is how a coupling fault in either direction gets caught.
The controller does not store millions of vectors. It stores this recipe: an address counter, a tiny state machine, and a comparator. That is why MBIST test data on the tester is small even when the SRAM is large. Many memories on one chip can run their controllers at the same time, which is how test time stays practical.
4. How ATPG works
ATPG means Automatic Test Pattern Generation. It does not walk a memory with read and write commands. A tool searches for input combinations that make a faulty gate disagree with a good gate.
Stuck-at-0 on an AND gate
assign y = a & b; Suppose input a is stuck at 0. Only one pattern shows it.
| a | b | Good Y | Faulty Y | Detected? |
|---|---|---|---|---|
| 0 | 0 | 0 | 0 | No |
| 0 | 1 | 0 | 0 | No |
| 1 | 0 | 0 | 0 | No |
| 1 | 1 | 1 | 0 | Yes |
The useful pattern is a = 1, b = 1. A good chip says Y = 1. A chip with a stuck at 0 says Y = 0. That mismatch is the detection.
What scan does
Slide the pattern into scan flip-flops.
Let the real logic run for one clock and save the result.
Slide that result back to the tester.
Does it match the good-chip answer?
4.5 Why ATPG cannot replace MBIST
This is the question behind most “MBIST vs ATPG” searches. Scan ATPG is excellent at gates. It is the wrong tool for the array inside an SRAM macro.
- No scan flop per cell. A scan chain is a shift register of flip-flops. An SRAM bitcell is a latch made of a few transistors, not a scan flip-flop. You cannot shift a 1 into bit 3 of address 2 through scan.
- Different faults. ATPG’s stuck-at model is “this net is shorted to 0 or 1.” A memory also fails when a neighbor write disturbs a cell, or when the decoder maps two addresses onto one row. Those are not gate-level stuck-at faults.
- Pattern size. Our toy RAM has 32 bits. A 1-megabit SRAM has about a million. Generating and storing a vector for every bit on the tester is slow and huge. A march recipe is a few states and a counter.
- Speed. The MBIST clock can run the memory at its functional rate and catch a cell that is too slow. A slow scan shift does not stress that timing.
What ATPG still tests around the memory: the collar logic, the mux that bypasses the RAM during scan, address and data flops outside the array, and the rest of the chip. The usual DFT split is MBIST for the array, ATPG for everything that was synthesized into scan.
5. MBIST vs ATPG
| Feature | MBIST | ATPG |
|---|---|---|
| Main target | Memory array | Digital logic |
| Typical pattern | Write then read sequences | Input test vectors |
| Who makes the pattern | On-chip MBIST controller | ATPG software (Tessent, TetraMAX, …) |
| Example fault | Cell stuck at 0 | Gate input stuck at 0 |
| How it is applied | March algorithm on the RAM ports | Scan shift, capture, shift out |
| Result | Pass or fail (often a fail address and bit) | Pass or fail (failing scan pattern and chain) |
| Test data size | Small — the algorithm is on chip | Large — vectors sit on the ATE |
| Typical algorithm | March C−, March LR, checkerboard | Stuck-at, transition, and sometimes path or cell-aware |
Remember MBIST
Write it → read it → compare it.
Question: can this memory keep the bits I stored?
Remember ATPG
Apply a pattern → capture → compare.
Question: does this logic answer like a good chip?
6. What happens in a real ASIC?
A chip has both memories and a sea of gates. DFT uses both tools. MBIST owns the SRAM macros. Scan and ATPG own the synthesized logic around them. A memory compiler often drops in the MBIST collar with the RAM. The exact hookup depends on the DFT flow, but the split of jobs stays the same.
During scan test the RAM is usually bypassed. A mux sends scan data around the memory so the chains on both sides still shift. That bypass tests the logic. It does not test the bitcells. MBIST is a separate mode: the controller owns address, data, and write-enable, runs the march, and reports pass or fail. Some flows also record the failing address so a repair step (BISR) can swap in a spare row or column. Repair is optional. Detection is not.
Interview FAQ
What is the difference between MBIST and ATPG?
MBIST is an on-chip memory test: write a pattern, read it back, compare. ATPG is off-chip pattern generation for logic, applied through scan shift and capture. Use MBIST on the SRAM array and ATPG on synthesized logic.
What is the difference between MBIST and LBIST?
Both are built-in self-test. MBIST targets memories with march algorithms. LBIST (logic BIST) targets random-logic cones with a pattern generator and a signature register. LBIST is not a substitute for a memory march.
Can ATPG test a RAM by itself?
It can toggle pins around the macro. It cannot march through every cell, and it does not model coupling or decoder faults. Memory test belongs to MBIST or to a dedicated algorithm on the tester.
Is write-0 / read-0 / write-1 / read-1 a full March C−?
No. That sequence catches a stuck cell. March C− also walks up and down with read-then-write pairs so a disturbed neighbor is observed. Learn the four-step picture first, then the six-element March C− above.
What does a failing MBIST tell you?
At minimum, fail. A useful controller also latches the address, the failing bit or bits, and which march element was running. That is the start of diagnosis and, on some SRAMs, of row or column repair.
Where should I read next?
BIST and March algorithms · ATPG and fault models · Scan chains · DFT course day 7 — MBIST