What is MBIST in simple words?

MBIST is a small circuit next to a memory. It writes a pattern, reads it back, and compares. If the bits that come back do not match the bits that were written, the memory failed.

What is ATPG in simple words?

ATPG is a tool that invents input patterns for logic gates and flip-flops. A good pattern makes a faulty chip produce a different output from a good chip, so the tester can see the defect.

Why not use ATPG alone to test RAM?

A memory has thousands of cells and special faults such as a cell stuck at 0, a slow cell, or two cells that disturb each other. March-style write and read sequences from an MBIST controller cover those faults more directly than random logic test vectors.

VLSI · DFT · Memory testing

MBIST vs ATPG

Same job, two different patients. MBIST checks whether a memory can store a bit and give it back. ATPG checks whether logic gates answer the way a good chip should. We start with a tiny RAM a school student can count.

1. Start with an 8-bit RAM

This example RAM has 4 addresses. Each address stores 8 bits. That is 4 × 8 = 32 storage bits. Real chips have millions of bits. The idea does not change.

Address	Stored data	Width
0	8 bits	one word
1	8 bits	one word
2	8 bits	one word
3	8 bits	one word

Normal RAM pins

Address — which word you want (0, 1, 2, or 3).
Write enable — 1 means “store this,” 0 means “just read.”
Write data — the 8 bits going in.
Read data — the 8 bits coming out.
Clock — the drumbeat. The write or read happens on a clock edge.

2. What is a memory fault?

A factory defect can freeze one tiny cell. The rest of the RAM still looks fine.

Stuck-at-0 on bit 3 of address 2

We write 11111111. Bit 3 cannot become 1. It stays 0. Counting from the right, bit 0 is the last digit.

Expected

11111111

Actual read

11110111

Expected ≠ read → fault detected. That one mismatch is the whole point of the test.

3. How MBIST works

MBIST means Memory Built-In Self-Test. A small controller sits next to the RAM. It writes patterns, reads them back, and compares. The outside tester does not have to invent every address.

MBIST controllerAddress, read/write, and the pattern.

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8-bit RAM4 words in this example.

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ComparatorExpected bits vs bits that came back.

Inside that controller you usually find:

an address counter (0, then 1, then 2, then 3)
a pattern generator (all zeros, all ones, or a march pattern)
a comparator
a small state machine that orders the steps
a pass/fail bit

A first sequence (not the full March algorithm)

1Write 0
Store 00000000 at every address.

2Read 0
Read every address. Each word must be 00000000.

3Write 1
Store 11111111 at every address.

4Read 1
Read every address. Each word must be 11111111.

Real MBIST uses longer marches (March C− and friends) so a cell is checked after its neighbors change. This four-step walk is enough to see a stuck-at-0 cell.

// Simplified MBIST idea — one address shown
WRITE_0:
    write_enable  = 1;
    write_data    = 8'b00000000;
    address       = addr;

READ_0:
    write_enable  = 0;
    expected_data = 8'b00000000;
    if (read_data != expected_data) fail = 1;

WRITE_1:
    write_enable  = 1;
    write_data    = 8'b11111111;

READ_1:
    write_enable  = 0;
    expected_data = 8'b11111111;
    if (read_data != expected_data) fail = 1;

Try it

Press a step. The table is the RAM.

Address	Stored bits	Check

4. How ATPG works

ATPG means Automatic Test Pattern Generation. It does not walk a memory with read and write commands. A tool searches for input combinations that make a faulty gate disagree with a good gate.

ATPG toolSearches for a useful pattern.

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Logic / scan chainShift the pattern in, capture the answer.

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CompareGood-chip answer vs this chip’s answer.

Stuck-at-0 on an AND gate

assign y = a & b; Suppose input a is stuck at 0. Only one pattern shows it.

a	b	Good Y	Detected?
0	0	0	No
0	1	0	No
1	0	0	No
1	1	1	Yes

The useful pattern is a = 1, b = 1. A good chip says Y = 1. A chip with a stuck at 0 says Y = 0. That mismatch is the detection.

What scan does

1Shift
Slide the pattern into scan flip-flops.

2Capture
Let the real logic run for one clock and save the result.

3Shift out
Slide that result back to the tester.

4Compare
Does it match the good-chip answer?

5. MBIST vs ATPG

Feature	MBIST	ATPG
Main target	Memory array	Digital logic
Typical pattern	Write then read sequences	Input test vectors
Who makes the pattern	On-chip MBIST controller	ATPG software (Tessent, TetraMAX, …)
Example fault	Cell stuck at 0	Gate input stuck at 0
How it is applied	March algorithm on the RAM ports	Scan shift, capture, shift out
Result	Pass or fail	Pass or fail

Remember MBIST

Write it → read it → compare it.

Question: can this memory keep the bits I stored?

Remember ATPG

Apply a pattern → capture → compare.

Question: does this logic answer like a good chip?

6. What happens in a real ASIC?

A chip has both memories and a sea of gates. DFT uses both tools. MBIST owns the SRAM macros. Scan and ATPG own the synthesized logic around them. A memory compiler often drops in the MBIST collar with the RAM. The exact hookup depends on the DFT flow, but the split of jobs stays the same.

SoCMemories + logic.

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MBISTTests the arrays.

Scan / ATPGTests the gates.

FAQ

Can ATPG test a RAM by itself?

It can toggle some pins, but it is a poor way to hunt cell faults. MBIST (or a memory test algorithm on an ATE) is built for address order, data backgrounds, and neighborhood effects.

Is this four-step test a full March C−?

No. March C− walks up and down the addresses with several read/write pairs so coupling faults show up. All-0 then all-1 is the picture you should learn first.

Where should I read next?

BIST and March algorithms · ATPG and fault models · Scan chains