Logic BIST
LBIST Architecture — PRPG & MISR
| Component | Type | Function | Typical Size |
|---|---|---|---|
| PRPG | LFSR (Linear Feedback Shift Register) | Generates maximal-length pseudo-random test patterns without external data | 32–64 bits |
| MISR | LFSR with multiple XOR inputs | Compacts all scan-chain response bits into a running signature | 32–64 bits |
| BIST Controller | FSM | Sequences BIST: reset, run N cycles, compare, report pass/fail | ~200–500 gates |
| Golden Signature | ROM / register | Known-good MISR output stored at design time for comparison | 32–64 bits |
Memory BIST
MBIST — March Algorithms for SRAM
| March Algorithm | Operations | Faults Detected | Complexity |
|---|---|---|---|
| March X | ↑(w0), ↑(r0,w1), ↓(r1,w0), ↓(r0) | SAF, TF, coupling (CF) | 4N |
| March C– | ↑(w0), ↑(r0,w1), ↑(r1,w0), ↓(r0,w1), ↓(r1,w0), ↑(r0) | SAF, TF, CF (comprehensive) | 10N |
| March Y | ↑(w0), ↑(r0,w1,r1), ↓(r1,w0,r0) | SAF, TF, CF, NPSF (basic) | 6N |
| MATS+ | ↑(w0), ↑(r0,w1), ↓(r1,w0) | SAF, TF | 4N (fast) |
| MARCH SS | Extended March C– variants | SAF, TF, CF, NPSF, PSAF | 22N (thorough) |
SAF=Stuck-At Fault, TF=Transition Fault, CF=Coupling Fault, NPSF=Neighborhood Pattern Sensitive Fault. N = number of memory cells. Industry standard for embedded SRAM: March C– or equivalent.
Memory Repair
SRAM Repair — Redundancy & Fuse Programming
| Step | What Happens | Tool / Method |
|---|---|---|
| 1. MBIST Test | March algorithm identifies all failing addresses (row + column coordinates) | MBIST controller records faulty address bitmap |
| 2. Repair Analysis | Algorithm determines minimum spare rows/columns to cover all faulty cells (NP-hard, heuristic for large arrays) | Repair algorithm (ATE software or on-chip) |
| 3. Spare Allocation | Map each faulty row/column to a specific spare row/column | Spare decoder in SRAM macros |
| 4. Fuse Programming | Blow eFuse bits to permanently redirect faulty address to spare (one-time programmable) | ATE fuse writer; eFuse controller on-chip |
| 5. Repair Verification | Re-run MBIST with fuses blown — verify all previously failing addresses now pass | MBIST re-run on ATE |
Comparison
LBIST vs MBIST
| Aspect | Logic BIST (LBIST) | Memory BIST (MBIST) |
|---|---|---|
| Target | Combinational and sequential logic (scan chain based) | Embedded SRAM, ROM, register file arrays |
| Pattern Gen | PRPG (LFSR) — pseudo-random | March algorithm controller (deterministic) |
| Response | MISR signature (compact) | Read data compared directly vs expected |
| Area overhead | ~5–10% (PRPG+MISR+controller) | ~5–15% of SRAM area (redundant rows/cols + controller) |
| Fault coverage | ~90% stuck-at (lower than ATPG deterministic) | Near-100% for SAF/TF with March C– |
| Test time | Fixed N pattern cycles (fast) | O(N) March steps — proportional to memory size |
| Use case | Field self-test, automotive in-system test, post-power-on boot test | Manufacturing test of embedded SRAM yield |
Interview Q&A
BIST Interview Questions
What is the difference between LBIST and MBIST?
LBIST (Logic BIST) tests combinational and sequential logic using an on-chip PRPG (LFSR-based pattern generator) feeding scan chains, and a MISR compacting responses into a signature. MBIST (Memory BIST) tests embedded memory arrays (SRAM, ROM) using a dedicated controller that applies March algorithms — sequential address-walking patterns that test each cell against its neighbors. The key difference: LBIST uses pseudo-random patterns sufficient for combinational logic; memory arrays need deterministic March patterns to detect coupling faults between adjacent cells.
What is MISR and how does it compact test responses?
MISR (Multiple-Input Signature Register) is an LFSR where each stage XORs in a scan chain output before feeding the next stage. It runs for N clock cycles, accumulating all N×(chain length) response bits into a single 32-bit (or 64-bit) signature. The probability that a defective circuit produces the correct signature by chance is 2⁻³² ≈ 10⁻¹⁰ — negligible. This "signature compaction" eliminates the need to store and compare millions of response bits; only the final signature is compared. The golden signature is simulated with a fault-free model and stored in ROM or OTP.
What is March C– and why is it used for SRAM testing?
March C– is a widely used SRAM test algorithm with 6 march elements and 10N operations (N = cells). It walks through all addresses ascending and descending, writing and reading 0s and 1s in each cell. This sequence detects: stuck-at faults (cell fixed at 0 or 1), transition faults (can't switch), read destructive faults, write disturb faults, and coupling faults (one cell corrupting its neighbor). March C– is preferred because it provides comprehensive fault coverage with reasonable test time — O(10N) is acceptable for SRAM arrays up to ~64 Mb.
How does SRAM repair with redundancy improve yield?
SRAM macros include spare rows and columns beyond the required capacity. When MBIST identifies faulty cells, the repair algorithm maps the faulty row/column to a spare by programming eFuse bits in the spare row/column decoder. This allows chips with a few SRAM bit failures to pass — improving die yield. For a 512KB SRAM with 1% of cells failing (a few thousand cells), adding 2–4 spare rows can repair ~90% of these failures, recovering the die that would otherwise be scrapped. Repair analysis runs on ATE and fuses are blown before the chip leaves the tester.
What is in-system LBIST and when is it used?
In-system LBIST (also called IJTAG or LBIST-at-startup) runs the BIST test during power-on initialization or periodically in the field — not just at manufacturing ATE. The chip self-tests its logic while the system is live. Used in: automotive (ISO 26262 requires periodic self-checking of safety-relevant logic), aerospace, server reliability (memory ECC + periodic LBIST on computation logic). The BIST controller is triggered by a watchdog or startup sequence; the result (PASS/FAIL) is reported via a status register or interrupt. The system halts or enters safe mode if BIST fails in the field.