Scan Flip-Flop
Scan-DFF — MUX-DFF Structure
Chain Architecture
Scan Chain — Shift & Capture Modes
| Mode | SE | What Happens | Purpose |
|---|---|---|---|
| Shift (Load) | 1 | Test pattern clocks in bit-by-bit through scan chain (N cycles for N FFs) | Load known test vector into all internal FFs |
| Capture | 0 | Circuit runs functionally for 1–2 clock cycles — response captured in SFFs | Observe circuit response to test stimulus |
| Shift (Unload) | 1 | Previous response shifts out while next test pattern shifts in simultaneously | Read captured response, load next pattern in parallel |
| Functional | 0 | Normal chip operation — scan infrastructure transparent | Normal product use |
Compression
Scan Compression — EDT / X-Compression
RTL Rules
RTL Coding Rules for DFT
| Rule | Problem if Violated | Correct Practice |
|---|---|---|
| No gated clocks in RTL | Combinational clock gating creates glitches; ATPG can't control gated FF | Use ICG (Integrated Clock Gate) cells inserted by synthesis tool; set SE on ICG |
| No internally generated resets | Reset tree not reachable from primary input — FF state uncontrollable during test | All resets must trace to primary input port; use reset synchronizer if async |
| No tri-state buses in core | Multiple drivers on a net — ATPG can't model correctly | Replace with MUX-based bus; tri-state only at I/O pads with output enable |
| SE port at top level | ATPG can't drive SE — can't enable scan shift | Expose SE as chip I/O pin; connect directly to all SFF SE pins |
| Never gate SE with logic | Logic may block SE from reaching FFs; false clock seen in test | Route SE directly from port to SFF; no AND/OR gates on SE path |
| Synchronous resets preferred | Async reset creates extra ATPG exemptions, increases uncontrollable FF count | Use synchronous reset; if async needed, model with ATPG exemption + reset_state |
| Avoid glitch-prone clock MUX | Clock glitches in test mode corrupt scan chain contents | Use glitch-free clock mux (ICG-based) with SE as select — safe during shift |
// BAD — gated clock in RTL (breaks DFT) always @(posedge (CLK & EN)) // ← synthesizer may create gated clock Q <= D; // GOOD — ICG cell (synthesizer inserts automatically) always @(posedge CLK) if (EN) Q <= D; // ← synthesizer infers ICG (enable register) // In SDC for DFT, connect SE to ICG cells: // set_case_analysis 0 [get_ports SCAN_EN] // functional mode analysis
Interview Q&A
Scan Chain Interview Questions
What is a scan flip-flop and how does it enable testing?
A scan-DFF adds a 2:1 MUX before the DFF's D input. When SE=0 (functional), data D propagates normally to Q. When SE=1 (scan), the scan input SI propagates to Q, making the FF part of a shift register. By chaining N scan-FFs (Q of FF[n] → SI of FF[n+1]), the entire chain forms a serial shift register accessible from the chip's scan_in/scan_out ports. This gives the tester direct read/write access to every internal FF without probing internal nodes.
What is the difference between shift mode and capture mode?
Shift mode (SE=1): the scan chain is a shift register. N clock pulses load the N-bit test vector — each bit from the ATPG pattern shifts in from scan_in and propagates through all FFs. Capture mode (SE=0): the circuit operates normally for 1–2 clock cycles. Combinational logic between FFs evaluates, and its output is captured (latched) into the next-stage SFF. Then shift mode resumes to unload the captured response through scan_out while simultaneously loading the next pattern. This shift-in/capture/shift-out cycle repeats for every test pattern.
What is scan compression and what compression ratio is typical?
Scan compression uses a decompressor (LFSR-based) between the external tester scan channels and internal scan chains. A small number of external channels (e.g., 8) drive the decompressor which fills many more internal chains (e.g., 800) in parallel. The output uses a MISR (multiple-input signature register) to compress all chain outputs into a compact signature. Compression ratio = internal chains / external channels = 800/8 = 100× in this example. Industry typical: 50–200×. This reduces tester data volume and test time by the compression ratio — critical for reducing manufacturing test cost.
Why is scan chain balancing important?
Test time is dominated by the longest scan chain (N clock cycles to shift in/out). If one chain has 5000 FFs and others have 100 FFs, the effective shift time per pattern is 5000 cycles even though shorter chains finish in 100. Balanced chains (e.g., 4 chains × 1250 FFs) reduce maximum chain length and total test time by 4×. The DFT tool also places consecutive FFs in a chain close together physically (short routing wires), reducing signal integrity risk and routing congestion from long scan paths.
What is an OCC (On-Chip Clock Controller) cell?
OCC provides precise clock control for scan testing. In shift mode, OCC routes a safe, slow test clock (from TCK or a divided source) to the SFFs — prevents glitches and clock conflicts. In capture mode, OCC allows exactly 1 or 2 pulses of the full-speed functional clock — necessary for at-speed transition fault testing (to detect delay defects that stuck-at tests miss). OCC has a feedback-based state machine to ensure glitch-free clock switching between test and functional clocks. Each asynchronous clock domain has its own OCC.
How does scan insertion affect timing and area?
Each DFF becomes a scan-DFF — area increases by ~10–15% due to the MUX logic added to each FF (or by using a physically larger scan-DFF cell from the standard cell library). Timing on the functional data path is slightly affected: the MUX adds ~0.05–0.1 ns to the DFF setup time. The scan path (SI→SO) doesn't need to meet functional timing — it only runs at the slow scan clock. Routing for the scan chain (SI/SO connections between consecutive FFs) consumes additional routing resources — typically 3–5% of total routing resources.