Question 1

What is Design for Testability (DFT)?

Accepted Answer

DFT is a set of design techniques that make manufactured ICs testable for manufacturing defects. The primary technique is scan insertion — flip-flops are converted to scan flip-flops and chained into a shift register, allowing ATPG-generated test patterns to reach internal nodes without physical probing. Additional DFT techniques include BIST (on-chip self-test), boundary scan (JTAG for board-level testing), and compression to reduce test time.

Question 2

What fault coverage is required for ASIC tapeout?

Accepted Answer

Industry standard requires ≥95% stuck-at fault coverage (SAFC) for most commercial designs, and ≥99% for automotive/safety-critical ICs (ISO 26262 ASIL-D). Transition fault coverage (for delay defects) is typically ≥80–90%. DFT sign-off includes: ATPG fault coverage report, test pattern count, test time estimate, and chip-level DRC on scan chain continuity.

Question 3

What is the difference between stuck-at and transition fault models?

Accepted Answer

Stuck-at (SA0/SA1) models a net permanently stuck at logic 0 or 1 due to manufacturing defects like shorts, opens, or oxide damage. It tests structural defects. Transition fault (slow-to-rise, slow-to-fall) models defects that cause a net to switch too slowly — caused by resistive opens, degraded drivers, or excessive capacitance. Transition tests are applied at-speed (full clock frequency) to detect delay defects that stuck-at patterns miss.

Question 4

What RTL rules must be followed for DFT?

Accepted Answer

Key RTL DFT rules: (1) No internally generated clocks — use ICG cells, not gated clocks in RTL; (2) No internal resets unrooted from primary input; (3) No tri-state buses in internal logic; (4) Scan enable (SE) accessible at top-level port; (5) Never gate SE with other logic — tie directly to scan flip-flop; (6) Use synchronous resets where possible; (7) Avoid asynchronous set/reset except where necessary; (8) Any clock mux must be glitch-free with SE as control.