Techniques that make manufactured ICs testable for defects — scan chains, ATPG, BIST, and JTAG boundary scan. Industry standard: ≥95% stuck-at fault coverage before tapeout.
A chip can be logically perfect and still ship broken, because manufacturing introduces physical defects — shorts, opens, stuck transistors. Design for Test is the discipline of adding structure to a design so that, after fabrication, automated equipment can quickly determine whether each individual die is good. Without DFT, testing a modern multi-million-gate chip would be effectively impossible.
The central idea is controllability and observability: to test an internal node you must be able to drive it to a known value and then observe the result at an output. DFT techniques insert hardware that makes deep internal logic reachable from the chip pins, turning an opaque black box into something an automatic test pattern generator can exercise thoroughly.
Strong DFT directly affects yield, test cost and field reliability, which is why it is woven into the RTL and physical-design flow rather than bolted on at the end. The topics here connect closely to scan-aware synthesis and timing, covered elsewhere in the VLSI section.