Core Concept
Stuck-At Fault — SA0 & SA1
Fault Models
VLSI Fault Models — Comparison
Stuck-At (SA0/SA1)
Dominant fault model
Models a net permanently stuck at 0 or 1 due to shorts/opens, oxide damage, metal bridging. Tested at slow speed. Detects most structural defects. Industry standard ≥95% SAFC for tapeout. Tools: slow-mode scan patterns.
Transition Delay (Slow-to-Rise / Slow-to-Fall)
At-speed testing
Models a net that transitions correctly but too slowly — resistive opens, extra capacitance, degraded transistors. Must be tested at full functional clock speed. Requires OCC for at-speed capture. Target: ≥80% TFC.
Bridge Fault
Net-to-net short
Models a short between two nets — wiring short, metal bridge, or electromigration. One net dominates the other (AND-bridging or OR-bridging depending on driver strengths). Requires neighbor-aware fault models. More difficult to test than stuck-at.
Cell-Aware Fault
Transistor-level defects
ISTAT (Intra-cell Stuck-at) models defects within a standard cell — resistive opens, partial bridges, parasitic interactions. Generated from transistor-level SPICE simulation. Captures defects not visible at gate level. Required for high-coverage automotive designs.
| Fault Model | Test Clock | Coverage Target | Tool Support |
|---|---|---|---|
| Stuck-At (SA0/SA1) | Slow (scan clock) | ≥95% commercial, ≥99% automotive | Tessent, TetraMAX, Encounter Test |
| Transition (TF) | At-speed (functional) | ≥80% transition fault coverage | Tessent, TetraMAX |
| Path Delay | At-speed | Critical paths only | Tessent TDRC |
| Bridge Fault | Slow or at-speed | Supplemental to stuck-at | Tessent (layout-aware) |
| Cell-Aware | Slow (intra-cell) | Required for automotive | Tessent Cell-Aware ATPG |
| IDDQ (current) | N/A (measure I_DD) | Catches opens, bridges | ATE current monitoring |
Algorithms
ATPG Algorithms — D-Algorithm, PODEM, FAN
| Algorithm | Approach | Key Innovation | Use Today |
|---|---|---|---|
| D-Algorithm (1966) | Boolean 5-value logic (0,1,D,D̄,X) backtracking over gate network | Introduced D-value to represent fault effect; classic foundation | Educational reference; replaced by faster methods |
| PODEM (1981) | Primary Input Oriented search — only assigns values at primary inputs, avoids internal contradictions | Dramatically reduced backtracking vs D-algorithm; handles reconvergent fanout | Still referenced; basis for modern tools |
| FAN (1983) | Fanout-Oriented ATPG — identifies unique sensitization (single path) first, then backtracks | Unique sensitization + head line identification reduces search space 10–100× | Foundation for Siemens Tessent, Synopsys TetraMAX |
| Modern SAT-based | Converts ATPG to Boolean SAT problem; SAT solver finds satisfying assignment | Complete — can prove untestability; handles large designs efficiently | Increasingly used for hard-to-test logic, sequential ATPG |
Fault Simulation
Fault Coverage Calculation
| Fault Category | Definition | Action |
|---|---|---|
| Detected (D) | ATPG found a test pattern that detects this fault — response differs from fault-free | Counts toward coverage — good |
| Possibly Detected (PD) | Pattern may detect fault but not proven — X-values on propagation path | Counts as partial — try to resolve X-sources |
| Untestable (UT) | Formally proven that no pattern can detect this fault — redundant logic | Removed from denominator in coverage calculation |
| Undetected (UD) | No pattern found — could be testability issue or truly untestable (not yet proven) | Investigate — add observability points or fix RTL testability |
| ATPG Abort (AU) | Search exceeded time/backtrack limit without finding or proving untestable | Must be <1% — increase effort or add constraints |
Interview Q&A
ATPG & Fault Model Interview Questions
What is the D-algorithm and what does the D value mean?
The D-algorithm uses a 5-valued logic system: 0, 1, D (fault-effect = 1 in good circuit, 0 in faulty), D̄ (= 0 in good, 1 in faulty), and X (unknown/unspecified). To test a stuck-at-0 fault on net N: assign D to N (good=1, faulty=0). Then propagate D through downstream gates to a primary output using Boolean logic rules. If D reaches a primary output, applying these input assignments will produce different outputs for good vs faulty circuit — the fault is detected. Backtracking is used when contradictions arise.
Why is 95% stuck-at fault coverage the industry threshold?
95% SAFC is an empirical threshold below which field defect escape rates (DPPM — defects per million) become unacceptably high. Statistical studies show that dropping from 95% to 90% coverage can multiply field failures by 10×. The exact threshold varies: 95% for standard commercial, 98–99% for high-reliability (server, networking), and 99%+ for automotive (ISO 26262 ASIL-D). Below the threshold, statistically too many defective dice pass ATE and reach end customers, causing recalls and reliability issues.
What is the difference between SA testing and transition fault testing?
SA (stuck-at) testing uses a slow, safe scan clock. It verifies structural correctness — that nets can switch between 0 and 1. SA passes even if a net switches but very slowly (degraded driver, resistive defect). Transition fault testing uses the full-speed functional clock for the capture phase (via OCC). It verifies speed — that nets transition fast enough (slow-to-rise STR, slow-to-fall STF). A resistive open defect might pass SA (net eventually reaches correct value) but fail TF (reaches it too late). Together, SA + TF testing catches both structural and speed defects.
What are cell-aware fault models?
Cell-aware (CA) ATPG models defects within a standard cell at the transistor level — resistive opens within cell, partial bridges between internal nodes, floating gate defects. The cell's SPICE netlist is simulated with each defect; the resulting behavior (possibly not a simple stuck-at) is characterized into per-cell fault dictionaries. CA ATPG is required for automotive-grade ASICs (ISO 26262) because some intra-cell defects produce behaviors (e.g., output stuck at intermediate voltage, or delayed transition) that stuck-at patterns miss. Tool: Mentor Tessent Cell-Aware ATPG.
What is ATPG fault abort and how do you reduce it?
ATPG abort (AU) occurs when the algorithm exceeds its backtrack/time limit without finding a test pattern or proving the fault untestable. Abort rate must be <1% for tapeout sign-off. Reduce abort by: (1) increasing ATPG effort (--effort high); (2) identifying non-DFT-compliant RTL (uncontrollable resets, gated clocks) that make faults hard to test — fix at RTL or add scan-enable constraints; (3) adding test points (observation points for observability, control points for controllability) in hard-to-test logic; (4) using sequential ATPG for faults requiring multiple capture cycles.