From a two-NAND SR latch all the way down to 20 CMOS transistors — how a rising clock edge captures one bit of data, why setup and hold time exist at silicon level, and what metastability actually looks like inside.
Before building a D flip-flop, you need to understand why it was invented. The simpler structures — SR latches and gated D latches — are level-sensitive: output can change any time the enable/clock signal is high. This creates a fundamental problem in synchronous digital design called transparent data corruption.
SR Latch (Unclocked)
Output Q responds immediately to S and R inputs. No clock. Any glitch on S or R ripples directly to Q. Useful for basic storage, not for clocked systems.
Gated D Latch (Level-Sensitive)
Output follows D whenever CLK=1 (transparent). When CLK=0, Q holds. Problem: if D changes while CLK=1, Q changes too — called transparency hazard.
D Flip-Flop (Edge-Triggered)
Q can only change at the exact rising edge of CLK. Between edges, Q is completely frozen regardless of D changes. This is what synchronous design requires.
Key insight: A D flip-flop samples D at one instant — the rising edge — and holds the result until the next rising edge. This predictable, once-per-cycle behavior is what makes Static Timing Analysis (STA) possible.
Section 02
Symbol, Truth Table & Characteristic Equation
The D flip-flop has a single data input D, a clock input CLK (shown with a triangle for edge-triggered), and outputs Q and its complement Q̄.
D flip-flop logic symbol. Triangle on CLK = edge-triggered.
D
CLK Edge
Q (next)
Q̄ (next)
0
↑ (posedge)
0
1
1
↑ (posedge)
1
0
X
CLK = 0 or 1
Q (hold)
Q̄ (hold)
Q(n+1) = D // Output simply copies D at posedge; holds otherwise
Section 03
Gate-Level Circuit — From SR Latch to D Flip-Flop
A D flip-flop is not designed from scratch — it evolves from simpler building blocks. Each step adds one feature. Understanding this evolution is the clearest way to see why the circuit is structured the way it is.
Step 1 — The SR NAND Latch (2 Gates)
The most fundamental storage element: two NAND gates with cross-coupled feedback. Output Q feeds back into G2, and Q̄ feeds back into G1. This creates a bistable circuit — once set or reset, it stays there until actively changed.
SR NAND latch — cross-coupled feedback makes it bistable. Active-low S̄ and R̄ inputs.
Problem with SR latch: It has a forbidden state (S̄=0, R̄=0 forces Q=Q̄=1, which is invalid). It's also completely unclocked — it responds instantly to any input change.
Step 2 — Gated D Latch (4 NAND Gates)
Add two steering NAND gates controlled by a clock (enable) signal. The key insight: tie S = D and R = D̄ (through an inverter). This eliminates the forbidden state — D can only be 0 or 1, never both, so S and R are always complementary.
Gated D latch — 4 NAND gates. Transparent when CLK=1, latches when CLK=0.
How it works: When CLK=1, both G1 and G2 pass their data — D flows through and Q follows D (transparent). When CLK=0, G1 and G2 both output 1 regardless of D — G3/G4 form a locked SR latch, holding the last value.
Step 3 — Master-Slave D Flip-Flop
Chain two gated D latches in series with inverted clock control. The first latch (master) is transparent when CLK=0. The second (slave) is transparent when CLK=1. They are never simultaneously transparent — this is the key. At the rising edge, the master closes (locks D in) and the slave opens (passes master's value to Q) in one atomic action.
Master-slave D flip-flop — two gated D latches with complementary clock. Never simultaneously transparent.
What Happens in Each Clock Phase
CLK = 0 (Low Phase)
Master: CLK̄ = 1 → Master TRANSPARENT — Qm follows D in real-time
Slave: CLK = 0 → Slave CLOSED — Q holds last captured value
Result: D changes ripple into master but Q is frozen
Setup window: D must settle before CLK rises
CLK ↑ (Rising Edge)
Master: CLK̄ = 0 → Master CLOSES — Qm locks the value of D at that instant
Result: Q takes on D's value from just before the edge
This is the entire "flip" — takes ~100 ps in real silicon
CLK = 1 (High Phase)
Master: Closed — still holding the captured value in Qm
Slave: TRANSPARENT — Q follows Qm (which is stable)
Result: Q is stable and valid throughout the high phase
CLK ↓ (Falling Edge)
Master: Re-opens — starts tracking new D value again
Slave: Closes — Q freezes at the current value
Result: Q holds; master prepares next data for next posedge
Section 04
The Edge-Triggering Mechanism — What Makes Posedge Special
In the master-slave design, the handoff between "master closes" and "slave opens" must happen at the same instant. But real gates have propagation delay. How does the circuit ensure both events happen at the rising edge and not gradually?
The answer is in the clock inverter. When CLK rises from 0→1, the CLK̄ signal fed to the master has a tiny propagation delay (≈20-50 ps through the inverter). This means:
1
CLK starts rising (0 → threshold)
Both master and slave transmission gates are still in their previous state. D is still propagating into the master storage node.
2
CLK crosses logic threshold (~Vdd/2)
The slave's clock input immediately sees this — the slave begins opening. Simultaneously, CLK̄ begins falling but is delayed by the inverter propagation time.
3
CLK̄ crosses threshold (~20-50 ps later)
Now the master's gate input (CLK̄) falls — the master closes. The master has already locked whatever D value was present. The slave is now fully open and presents Qm as Q.
4
Capture complete
The entire transition took ~50 ps. From D's perspective, it was captured at a single instant. That narrow window IS the setup/hold aperture — violate it and you risk metastability.
Internal waveforms — CLK̄ lags CLK by inverter delay. Qm locks before Q updates (slave propagation = clock-to-Q delay).
Section 05
CMOS Implementation — 20 Transistors Inside
In silicon, a gated D latch is not built from NAND gates — it's built from CMOS transmission gates and inverter pairs. This is faster, smaller, and far more power-efficient. Two such latches, clocked with complementary signals, form the master-slave D flip-flop.
The Transmission Gate (TG)
A transmission gate is simply an NMOS and PMOS transistor in parallel, sharing source/drain. One transistor's gate gets CLK, the other gets CLK̄. When both are ON simultaneously, the path conducts with very low resistance — nearly zero. When both are OFF, the path is open.
CMOS transmission gate — NMOS + PMOS in parallel. 2 transistors total. Conducts when CLK=1.
CMOS Latch = TG + Two Inverters + Feedback TG
One CMOS gated D latch uses 8 transistors: one input transmission gate (2T), two inverters forming the storage loop (4T), and one feedback transmission gate (2T) that keeps the loop active when the latch is closed.
TG_in (Input Gate)
Controlled by CLK (NMOS) and CLK̄ (PMOS). Conducts D into latch when CLK=0 (master) or CLK=1 (slave). 2 transistors.
INV1 (Drive Inverter)
Inverts D to produce the first stored signal. Its output is the internal node that gets locked at the clock edge. 2 transistors.
INV2 (Feedback Inverter)
Re-inverts INV1's output to restore D polarity and drives feedback. INV1 + INV2 form a cross-coupled pair — bistable memory. 2 transistors.
TG_fb (Feedback Gate)
Controlled by CLK̄ (NMOS) and CLK (PMOS) — always opposite of TG_in. When TG_in is open, TG_fb is closed, completing the feedback loop to hold state. 2 transistors.
TG_m_in: CLK̄=0 → NMOS OFF, PMOS OFF → OPEN — D is disconnected from master
TG_m_fb: CLK=1 → CLOSED → INV1–INV2 loop is active — node voltage held by cross-coupled inverters
Slave TG: CLK=1 → NMOS ON, PMOS ON → CLOSED — Qm passes through to Q
Slave feedback: OPEN — slave is transparent, not latching
Why the feedback transmission gate matters: When TG_in closes and disconnects D, the storage node is floating. Without TG_fb completing the INV1→INV2→INV1 loop, charge leaks off the gate capacitance and the bit is lost in nanoseconds. TG_fb is always the opposite state of TG_in.
CMOS State Viewer — Toggle Clock Phase
Phase: CLK LOW — Master transparent
Section 06
Timing Parameters — Setup, Hold, tCQ
Four timing parameters completely characterize a D flip-flop's behavior. They arise directly from the transistor-level physics seen in Section 05. Understanding why they exist is far more useful than memorizing their names.
Parameter
Symbol
Typical (28nm)
Physical Cause
Setup Time
t_su
50–150 ps
D must propagate through TG_in and settle at the INV1 input node before TG_in closes. If the node isn't settled, an intermediate voltage gets latched.
Hold Time
t_h
0–30 ps
After CLK rises, TG_in closes — but has finite turn-off delay (~20 ps). If D changes during this window, it can still perturb the node through the partially-conducting TG. D must remain stable until TG is fully OFF.
Clock-to-Q Delay
t_CQ
80–200 ps
After posedge, slave TG_s_in closes (briefly) and then the slave inverter chain drives Q. t_CQ = slave TG propagation + INV3 + INV4 output drive.
Min Pulse Width
t_pw
100–300 ps
CLK must stay high long enough for the slave latch to fully resolve its output. Narrow pulses can cause incomplete transfer.
D must be stable from t_su before the rising edge to t_h after it. Q changes t_CQ after the edge.
STA Setup Check: T_clk ≥ t_CQ + t_logic + t_su + t_skew STA Hold Check: t_CQ + t_logic_min ≥ t_h + t_skew
These two equations are exactly what a Static Timing Analyzer (like PrimeTime) evaluates on every register-to-register path in a chip. Setup failures reduce your maximum clock frequency; hold failures can cause functional errors at any frequency.
Section 07
Metastability — When the Flip-Flop Gets Stuck
If D changes inside the aperture window (within t_su before or t_h after the rising edge), the master latch captures an intermediate voltage — neither a clean 0 nor a clean 1. The cross-coupled inverter pair (INV1–INV2) has three equilibrium points:
Stable State: Q = 0
INV1 output = Vdd (high), INV2 output = 0 (low). Both transistors are deep in saturation. Strong restoring force. Extremely stable.
Metastable State: Q ≈ Vdd/2
Both INV1 and INV2 outputs hover near Vdd/2 — the unstable equilibrium. Any tiny perturbation tips it one way. Can persist for nanoseconds or longer before resolving.
Stable State: Q = 1
INV1 output = 0 (low), INV2 output = Vdd (high). Opposite configuration. Just as stable as Q = 0.
The dangerous part: In metastability, the flip-flop doesn't output 0 or 1 — it outputs Vdd/2. This intermediate voltage can be interpreted differently by different gates downstream, causing half your logic to see a 0 and the other half to see a 1. The entire synchronous system falls apart.
Resolution Time and MTBF
The metastable state resolves exponentially — the time to resolve follows:
P(still metastable after time τ) = exp(−τ / τ₀)
MTBF = exp(T_resolve / τ₀) / (f_clk × f_data × T_window)
Where τ₀ is the flip-flop's metastability time constant (process-dependent, typically 20–50 ps), T_resolve is how long downstream logic waits before sampling (= one clock period for synchronizers). A proper 2-FF synchronizer gives t_resolve ≈ one full clock period — enough to reduce metastability probability to once per 10⁹ years for typical data rates.
In practice: You cannot eliminate metastability for truly asynchronous inputs (CDC crossings, button presses, external signals). You manage it with synchronizer circuits — a chain of flip-flops that gives the metastable output time to resolve before any logic consumes it.
Section 08 · Lab
Interactive Lab — D Flip-Flop Waveform Simulator
Toggle D and step the clock manually, or enable auto-run. Watch how Q captures D only on the rising edge. Change D near a clock edge to trigger a metastability warning — the aperture window is highlighted in amber on every posedge.