The complete reference — from the bistable SR latch to edge-triggered VLSI storage. SR, JK, D, T flip-flops, master-slave, timing, metastability, and real-world CPU applications.
A flip-flop is a bistable multivibrator — a sequential circuit with exactly two stable states (0 and 1). Unlike combinational gates, a flip-flop retains its output until told to change by a clock edge. This ability to store one bit is the foundation of all digital memory.
Every processor — from an 8 MHz microcontroller to a 3 GHz server CPU — is composed of millions of flip-flops forming registers, pipeline stages, FSMs, FIFOs, and synchronizers. Understanding flip-flops deeply is not optional for a digital designer.
A single flip-flop stores 1 bit. An array of 64 flip-flops sharing a clock forms a 64-bit register — the fundamental storage unit in a 64-bit CPU.
The term flip-flop comes from the two-phase switching behavior described by Eccles and Jordan in 1918 using vacuum tubes. Modern CMOS implementations consume nanowatts in sub-10 nm nodes.
Every digital circuit belongs to one of two categories. Combinational: output depends only on current input, no memory — adders, MUXes, encoders. Sequential: output depends on current input AND stored state — counters, registers, FSMs.
| Property | Combinational | Sequential |
|---|---|---|
| Memory | None | Flip-flops / latches |
| Clock | Not required | Required (sync) |
| Feedback | Never | Always |
| Output depends on | Present input only | Input + past state |
| Examples | Adder, MUX, Encoder | Counter, Register, FSM |
A latch is level-triggered — it's transparent when the enable is active; any input change propagates directly to the output. A flip-flop is edge-triggered — it samples input only at the clock transition instant.
VLSI synchronous design always uses edge-triggered flip-flops. Latches are used in specific low-power or half-cycle-borrowing scenarios but require specialised timing analysis. Default to flip-flops in RTL.
The SR latch is the simplest bistable and the conceptual core of every flip-flop. Two cross-coupled NOR (or NAND) gates create a feedback loop sustaining a 0 or 1 with no clock.
| S | R | Q (next) | Q' (next) | Action |
|---|---|---|---|---|
| 0 | 0 | Q | Q' | HOLD |
| 0 | 1 | 0 | 1 | RESET |
| 1 | 0 | 1 | 0 | SET |
| 1 | 1 | 0 | 0 | INVALID |
The forbidden input (S=R=1 for NOR; S̄=R̄=0 for NAND) must be avoided. When simultaneously removed, the final state is unpredictable — this is the critical race condition.
Adding a clock enable gates S and R through AND gates before the NOR pair. When CLK=0 both inputs are forced 0 (HOLD). When CLK=1 S and R can change state. The forbidden S=R=1 condition still exists — this is mostly a pedagogical stepping stone toward JK and D types.
The JK flip-flop solves the SR forbidden state by defining J=K=1 as toggle. Feedback from Q back to K's AND gate and Q' back to J's AND gate ensures only the currently-OFF path activates when J=K=1.
| J | K | Q(n) | Q(n+1) | Operation |
|---|---|---|---|---|
| 0 | 0 | X | Q | HOLD |
| 0 | 1 | X | 0 | RESET |
| 1 | 0 | X | 1 | SET |
| 1 | 1 | 0 | 1 | TOGGLE |
| 1 | 1 | 1 | 0 | TOGGLE |
When J=K=1 and the clock stays HIGH longer than the FF's propagation delay, the toggled output feeds back and triggers another toggle — oscillating within a single clock pulse. Final state is indeterminate.
Occurs when J=K=1 and clock pulse width > propagation delay. Solution: master-slave architecture or edge-triggered design.
Two cascaded latches operating on complementary clock phases eliminate race-around. The Master reads inputs; the Slave transfers to the final output — in separate clock phases so feedback never completes within one phase.
Master-slave JK FFs are pulse-triggered — they sample throughout the HIGH phase. Modern CMOS FFs are truly edge-triggered, sampling only at the clock transition instant for superior noise immunity.
Derived from JK by permanently wiring K = J'. On every rising clock edge, Q follows D. No forbidden state, no toggle ambiguity, no race condition — and the simplest possible RTL model.
| CLK Edge | D | Q(n+1) | Action |
|---|---|---|---|
| ↑ Rising | 0 | 0 | RESET |
| ↑ Rising | 1 | 1 | SET |
| No edge | X | Q(n) | HOLD |
Real VLSI D FFs include asynchronous Preset (PRE) and Clear (CLR) overrides for power-on reset. Scan FFs (SDFF) add a 2:1 MUX before D — SE=0: normal operation; SE=1: scan chain input. This enables ATPG in production testing.
JK with J=K=T. When T=1 on a clock edge, Q toggles; T=0 holds. Natural counter cell — with T=1 always it divides the clock by 2. Cascading N stages gives ÷2ᴺ.
| T | Q(n) | Q(n+1) | Action |
|---|---|---|---|
| 0 | X | Q | HOLD |
| 1 | 0 | 1 | TOGGLE |
| 1 | 1 | 0 | TOGGLE |
Used in PLL feedback dividers, UART baud generators, watch crystal dividers (32,768 Hz → 1 Hz), and ripple counters.
| Feature | SR | JK | D | T |
|---|---|---|---|---|
| Inputs | S, R | J, K | D | T |
| Forbidden State | S=R=1 | None | None | None |
| Characteristic Eq. | S+R'Q | JQ'+K'Q | D | T⊕Q |
| Toggle Capable | No | J=K=1 | No | T=1 |
| VLSI Usage | Rare | Moderate | Dominant | Common |
Setup Time (tsu): Data must be stable this long before the clock edge. In 28nm, typically 20–50 ps. Violation can cause incorrect latching or metastability.
Hold Time (th): Data must remain stable this long after the clock edge. Cannot be fixed by reducing clock frequency — must insert delay buffers on the violating path.
Clock-to-Q (tcq): Time from clock edge until Q settles at its new value. Bounds maximum frequency:
Synopsys PrimeTime and Cadence Tempus verify timing across all PVT corners. Positive slack = constraint met; negative slack = timing violation to fix before tapeout.
Metastability occurs when data transitions within the setup-hold window. The flip-flop's bistable element is poised at an unstable equilibrium — output voltage is between valid 0 and 1. It eventually resolves but the time follows an exponential distribution — always a non-zero probability of persisting past any deadline.
Unavoidable when capturing asynchronous signals or crossing between unrelated clock domains. Cannot be eliminated — only statistically suppressed.
Chain 2–3 D FFs in the destination domain. The first may go metastable, but given one full clock period the probability of not resolving before the second FF samples is extremely small.
Where τ ≈ 20–100 ps in deep submicron CMOS. A 3-FF synchronizer in 28nm at 1 GHz can achieve MTBF exceeding 10 million years.
Express the target FF's characteristic equation in terms of the available FF's excitation inputs using excitation tables.
| Goal | Available FF | Required Logic |
|---|---|---|
| D from JK | JK | J = D, K = D' |
| T from JK | JK | J = T, K = T |
| SR from JK | JK | J = S, K = R |
| D from T | T | T = D ⊕ Q |
| JK from D | D | D = JQ' + K'Q |
| T from D | D | D = T ⊕ Q |
A CPU's 64-bit × 32-register file = 2,048 D flip-flops with shared write clocks and MUX-based read ports.
IF→ID→EX→MEM→WB stage barriers are D flip-flop arrays holding partial results between clock cycles.
Ripple counters use T FFs in series. Synchronous counters add carry-lookahead for GHz-range operation.
SIPO / PISO / SISO chains of D FFs. Used in SPI/I²C/UART, barrel shifters, and LFSR-based PRBS generators.
Moore and Mealy FSMs hold current state in D FFs. Next-state combinational logic feeds back to D inputs.
Two-flop synchronizers pass signals safely between different clock domains, suppressing metastability to sub-PPB.
Scan FFs link into a shift register for ATPG. A 1M FF chip tested in milliseconds at 100 MHz scan rate.
D latches hold row addresses during RAS cycles, enabling full-row access with minimal address pin count.
The Apple M4 (3nm TSMC, ~28B transistors) allocates a significant fraction to flip-flops across 8-wide OOO pipelines, 32 MB L3 tag arrays, 192-entry reorder buffers, and scan chains. Clock gating and power gating keep dynamic power (C·V²·f) within thermal limits.
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