RISC-V is an open instruction set architecture (ISA): a public rulebook that says which instructions a compatible processor must understand. It is not a single chip, company, or operating system. Many companies and universities build their own RISC-V cores. The ISA is royalty-free; designing and manufacturing a chip still costs money.

RV32I is the 32-bit RISC-V base integer instruction set. It defines 32 registers that are 32 bits wide, a 32-bit address space, and the core integer, load, store, branch and jump instructions. Optional letters such as M, A, F, D and C add multiply, atomics, floating point and compressed 16-bit encodings.

What is the difference between registers and memory in RISC-V?

Registers sit inside the CPU and hold the handful of numbers the processor is using right now. Memory (RAM) is a large numbered warehouse of bytes. RISC-V is a load-store architecture: add, subtract, and logic only operate on registers. Load instructions copy from memory into a register; store instructions copy from a register into memory.

Is RISC-V the same as a RISC-V chip?

No. RISC-V is the language. A chip is one implementation of that language. Two RISC-V chips can both run the same RV32I program and still differ in speed, caches, pipelines, and extra custom instructions.

Does RISC-V replace ARM or Intel?

Not as a wholesale replacement in phones and PCs in the near term. RISC-V is growing in microcontrollers, custom silicon, research, and some laptops and SoCs, while ARM and x86 remain dominant in their established markets.

OPEN ISA · BEGINNER GUIDE

What Is RISC-V? How the Architecture Works

Q: How does RISC-V work?

A RISC-V CPU repeatedly fetches an instruction from memory at the program-counter address, decodes the opcode and register numbers, then executes it. Arithmetic uses the integer registers. Data in RAM is moved with load and store instructions. After a 32-bit instruction the PC usually advances by 4 bytes.

Q: How many registers does RISC-V have?

The common base integer ISA (RV32I / RV64I) has 32 general-purpose integer registers named x0 through x31. x0 is hardwired to zero. The program counter (PC) is a separate special register, not one of the 32. Tiny RV32E cores use 16 integer registers (x0–x15). Optional floating-point extensions add a second file of 32 f registers.

Q: Is RISC-V open source?

The RISC-V ISA is an open, royalty-free standard. Anyone may implement it. Individual cores and chips may be open-source RTL, proprietary IP, or a mix. Open ISA does not mean the silicon or tools are free.

By EcrioniX · 13 Sep 2026 · ~18 min read

What is RISC-V? It is an open instruction set architecture (ISA) — the public grammar a CPU uses, not a brand of chip. This guide shows how RISC-V works in plain language: the RISC-V register file (x0–x31), load-store memory, the program counter, and the fetch–decode–execute loop. Aimed at school students and first-year engineers, without the usual myths.

Read this first so we do not mislead you

RISC-V is not a chip you buy, not an operating system, and not “free computers.” It is an instruction set architecture (ISA) — the list of instructions and registers a compatible CPU must provide. SiFive, Andes, Espressif, IIT Madras SHAKTI, and many others each build their own chips that speak RISC-V. Two RISC-V chips can both run the same simple program and still be totally different inside (speed, caches, extra features).

1. What is RISC-V? An open instruction set architecture

Software is a list of tiny orders: “add these two numbers,” “load a value from memory,” “if this is zero, jump elsewhere.” A processor can only obey orders it was built to understand. That shared vocabulary is the ISA.

English is not a novel. RISC-V is not a Raspberry Pi. English is the grammar; novels are what people write with it. RISC-V is the grammar; chips are the novels. Born at UC Berkeley and now maintained by RISC-V International, the spec is open: anyone may implement the standard instructions without paying a royalty for the ISA itself. (You still pay for engineers, tools, and the factory that prints silicon.)

Same language, many speakers. Compatibility is about the ISA, not identical wiring inside the chip.

2. What RISC means in RISC-V architecture

RISC stands for Reduced Instruction Set Computer. The name is historical. It does not mean “this CPU has almost no instructions” or “it is weaker than Intel.” Modern RISC-V, with optional extensions, can have a large catalogue.

The useful meaning of RISC here is a style:

Load–store. Maths happens in registers. Memory is only touched by load and store instructions.
Regular encoding. Base instructions are a fixed 32 bits wide (optional compressed 16-bit forms exist — see later).
Lots of registers. Keep working values close to the ALU instead of bouncing to RAM every step.
Simple jobs per instruction. One instruction does one clear thing, which makes pipelined hardware easier to design.

ARM is also a RISC family. x86 is a CISC family with a more irregular encoding. That comparison is a business and ecosystem story as much as a technical one. For this page we stay inside RISC-V.

3. How a RISC-V CPU works: fetch, decode, execute

A RISC-V hart (hardware thread — think “one core running one stream of instructions”) repeats three ideas forever until you cut power:

STEP 1

Fetch

Read the next instruction from memory at the address in the program counter (PC).

STEP 2

Decode

Split the 32-bit word into opcode, register numbers, and immediates. Decide what the ALU and memory should do.

STEP 3

Execute

Add, compare, load, store, or jump. Then update the PC to the next instruction (usually PC + 4 for a 32-bit instruction).

A classroom drawing is a single-cycle core: one instruction finishes every clock. Fast chips use a pipeline (several instructions in flight) and caches. Those are implementation tricks. The ISA still says the same thing: “after this ADD, x7 holds the sum.” Students should learn the ISA first; pipelines come later in RISC-V from Scratch.

The PC is “which line of the program am I on?” It is not one of the 32 x-registers.

4. RISC-V registers (x0–x31) explained

A register is a tiny, extremely fast box inside the processor that holds one number. In RV32I that number is 32 bits (XLEN = 32). In RV64I the same 32 names hold 64-bit values (XLEN = 64). Do not confuse “32 registers” with “32 bits of storage.” You have 32 boxes; each box is 32 or 64 bits wide.

Desk vs warehouse

Registers are the papers on your desk — few, instant to grab. Memory is the warehouse down the hall — huge, but you walk to get a box. CPUs are fast because they do homework on the desk and only visit the warehouse when they must.

The 32 integer registers (x0–x31)

The base integer ISA gives x0 … x31. Software also uses friendly ABI names from the standard calling convention (who keeps which register across a function call). Same silicon, two labels.

Number	ABI name	Job (standard ABI)	Kept across a function call?
`x0`	`zero`	Always reads as 0. Writes are discarded.	—
`x1`	`ra`	Return address (where to jump back after a call)	No (caller-saved)
`x2`	`sp`	Stack pointer — top of the current stack	Yes (callee-saved)
`x3`	`gp`	Global pointer (tooling; not a general scratch pad)	—
`x4`	`tp`	Thread pointer	—
`x5–x7`	`t0–t2`	Temporaries	No
`x8–x9`	`s0–s1`	Saved registers; `s0` may be the frame pointer	Yes
`x10–x17`	`a0–a7`	Arguments and return values	No
`x18–x27`	`s2–s11`	More saved registers	Yes
`x28–x31`	`t3–t6`	More temporaries	No

x0 is the clever trick. Hardware wires it to zero. Reading x0 always gives 0. Writing x0 does nothing useful (the write is ignored). That gives a free constant 0 and lets one encoding do several jobs: copy with add rd, rs, x0, or throw a result away by writing x0.

Not every RISC-V chip has 32 integer registers

The embedded variant RV32E has only x0–x15 (16 integer registers) to save silicon. The ABI for that case is different (ILP32E). If a tutorial says “always 32,” that is RV32I/RV64I, not every possible RISC-V core.

Registers that are not x0–x31

Program counter (PC). Holds the address of the current (or next) instruction. You cannot add into the PC like a normal x-register. Jumps and branches change it.
CSRs (Control and Status Registers). Extra named registers for traps, timers, privilege. Used by system software, not by a first “hello world” ADD.
Floating-point f0–f31. Only if the chip implements the F and/or D extensions. Integer RISC-V does not magically have IEEE floats.
Vector registers. Only with the V extension. Many microcontrollers have none.

5. RISC-V memory: load and store

RISC-V memory is byte-addressed: address 0 is one byte, address 1 is the next byte, and so on. RV32I offers a 32-bit address space in the ISA (up to 4 GiB of addressable locations). A cheap microcontroller may only wire a few kilobytes of real RAM into part of that space. The rest of the map might be empty, or hold memory-mapped UART, timers, and flash. The spec calls this an execution environment question: the ISA says how loads work; the board says which addresses are legal.

There is no add that takes a RAM address as an operand. You load, then add, then store if you must write back.

Loads and stores you will actually see

Address = register rs1 plus a 12-bit signed offset. Then:

lw / sw — 32-bit word (RV32)
lh / lhu / sh — 16-bit halfword (signed or zero-extended on load)
lb / lbu / sb — 8-bit byte

RV64 adds ld/sd for 64-bit values, and lwu for a 32-bit load zero-extended into a 64-bit register.

Endianness, alignment, caches — stay honest

Endianness. The ISA allows the execution environment to choose. Almost all RISC-V Linux and GCC targets you will meet are little-endian (the least-significant byte sits at the lowest address). Do not memorise “RISC-V is always little-endian” as a law of physics — it is the software world you will actually use.
Alignment. A 32-bit word naturally wants an address divisible by 4. Some cores handle misaligned accesses in hardware; others trap and let software fix it. A beginner program should keep words aligned.
Caches. L1/L2 caches are not extra registers in the ISA. They are a speed trick so the warehouse feels closer. A correct program should behave as if it talked to a simple memory (with extra rules when multiple cores share RAM — RISC-V’s default ordering model is called RVWMO, which is a later topic).
Instruction vs data. The programmer’s address space is normally one map (von Neumann-style). Many chips still have separate instruction and data caches or tightly-coupled memories. That is microarchitecture, not a second secret ISA.

The stack is just memory plus `sp`

The stack is not a special RAM chip. It is a region of ordinary memory. Register x2/sp holds the current top. Function calls push return addresses and spilled registers, then pop them. Convention (not a transistor law) says the stack grows toward lower addresses on standard ABI RISC-V.

6. RISC-V assembly example: 10 + 32 = 42

Here is a complete thought, first in friendly ABI names, then in the real instructions an assembler typically emits. li is a pseudo-instruction: the assembler may turn it into addi when the constant fits in 12 bits.

sum.s — RISC-V assembly

        .text
        .globl  _start
_start:
        li      t0, 10          # t0 is x5; assembler → addi x5, x0, 10
        li      t1, 32          # t1 is x6
        add     t2, t0, t1      # t2 is x7; t2 = 42
        # In a real board you would then ecall or store the result.
        # This snippet only shows the ALU path.

Same idea with numbered registers

        addi    x5, x0, 10
        addi    x6, x0, 32
        add     x7, x5, x6      # x7 = 42

What the hardware does, in order:

Fetch the addi word from the address in the PC.
Decode: opcode says “I-type ALU,” rd = x5, rs1 = x0, immediate = 10.
Read x0 (which is 0), add 10, write 10 into x5. Ignore any write if rd were x0.
PC becomes PC + 4. Repeat for the second addi, then for add which reads two registers and writes x7.

To put 42 into RAM you would add something like sw t2, 0(sp) after setting sp to a valid RAM address. Without a valid address, a real core raises an exception — another reason “it assembled” is not the same as “it ran.”

Instruction formats in one sentence

RV32I uses a few 32-bit layouts (R, I, S, B, U, J) so decode hardware stays regular. add is R-type (three registers). addi and lw are I-type. sw is S-type. Branches are B-type. You do not need to memorise bit numbers to understand the idea; you do need them if you build a decoder in Verilog.

7. RV32I and RISC-V extensions (I, M, A, F, D, C, V)

RISC-V is modular. A name like RV32IMAC is a shopping list:

Letter	What it adds	Do all chips have it?
I	Base integer (the heart: add, load/store, branches, jumps)	Required for “RV32I” / “RV64I”
M	Multiply and divide	No — tiny cores may omit it
A	Atomic memory operations (for locks between cores)	No
F / D	Single / double-precision floating point + `f` registers	No
C	Compressed 16-bit encodings of common ops (denser code)	Very common, still optional
V	Vector (SIMD-style) operations	No — mostly bigger / newer cores

Companies may also add custom instructions for crypto or AI. That is allowed. Software that uses a custom opcode will not run on a core that lacks it. Portable teaching code sticks to I (and maybe M and C).

Privilege in one paragraph: Machine mode (M) is the “boss” mode every core has. User mode (U) is for apps. Supervisor mode (S) is what Linux needs. A microcontroller running a while-loop in M-mode is still honest RISC-V; it is just not a Linux laptop.

8. RISC-V myths vs facts

Myth	Accurate version
“RISC-V is a processor like Snapdragon.”	RISC-V is the ISA. Snapdragon is a product family. Some SoCs include RISC-V cores; many phones are still ARM.
“Open means the chip is free.”	The spec is royalty-free. Silicon, verification, and software still cost real money.
“32 registers means 32 bits total.”	32 boxes, each 32-bit (RV32) or 64-bit (RV64).
“Registers are a kind of RAM.”	Registers are on-core storage. RAM is a separate, much larger array of bytes.
“RISC-V has no multiply.”	The I base has no multiply. The M extension does. Check the chip’s string (RV32IM…).
“It will replace ARM and Intel next year.”	It is growing in MCUs, custom chips, and research. Dominant phone/PC ISAs do not vanish on a slogan.

What you should remember

RISC-V is an open ISA — a language — implemented by many chips.
RV32I has 32 integer registers; x0 is always zero; the PC is separate.
Load-store: ALU on registers; lw/sw (and friends) for memory.
Memory is a byte array; the stack is memory plus sp; caches are speed, not extra ISA registers.
Extensions (M, F, C, V…) are optional. Always read the core’s ISA string.

RISC-V FAQ

What is RISC-V?

An open instruction set architecture: the public list of instructions and registers a compatible CPU must provide. Not a single brand of chip and not an OS.

How does RISC-V work?

The core fetches an instruction from the PC address, decodes it, then executes it. Maths uses registers. RAM is only touched by load and store. After a 32-bit instruction the PC usually adds 4.

What is RV32I?

The 32-bit RISC-V base integer ISA: 32 registers that are 32 bits wide, plus integer ALU, loads/stores, branches and jumps. Extra letters (M, F, C…) are optional kits.

How many registers does RISC-V have?

RV32I/RV64I: 32 integer registers x0–x31 plus a separate PC. RV32E: 16 integer registers. Optional F/D add 32 floating-point registers.

Why is x0 always zero?

It is hardwired. Reads return 0; writes are ignored. That gives a free constant and simplifies encodings (copy, compare to zero, discard results).

Is RISC-V open source?

The ISA is an open royalty-free standard. A given chip’s RTL might be open or proprietary. Open spec ≠ free silicon.

Where is the program stored?

As bytes in memory (often flash or RAM). The PC holds the address of the instruction being fetched. After a 32-bit instruction, the PC normally moves forward by 4 bytes.

Is RISC-V better than ARM?

Different question: RISC-V wins on an open, modular spec; ARM wins on a huge mature software and core ecosystem. See our RISC-V vs ARM article for a fair comparison.

Can I build a RISC-V CPU?

Yes — the ISA is open. Our free course RISC-V from Scratch builds a teaching RV32I core in Verilog. That is a learning core, not a phone SoC.