The chip inside your phone started as a pile of sand on a beach. What happens between that sand and the finished processor — with 20 billion transistors each smaller than a virus — is the most precise manufacturing process in human history. This is the complete visual guide to how TSMC does it.
Common beach sand is silicon dioxide (SiO₂). That oxygen has to go. TSMC's supply chain starts at specialized quartz mines — not beach sand, but high-purity quartzite rock that is ~99% SiO₂.
The quartzite is heated in an electric arc furnace with carbon to reduce it: SiO₂ + C → Si + CO₂. The result is metallurgical-grade silicon — about 98-99% pure. That's not nearly good enough for transistors. It then goes through the Siemens process: the silicon reacts with hydrogen chloride to form trichlorosilane gas, which is distilled and then decomposed to deposit ultra-pure silicon onto seed rods. The result: electronic-grade silicon at 99.9999999% purity (9 nines). A single stray atom of iron in a trillion silicon atoms would ruin the chip.
A blank wafer is just a flat disc of silicon. To make transistors, you need to pattern it — define which areas get doped, oxidized, or etched. That patterning is done by photolithography: using light to print a pattern from a mask onto the wafer, the same way a photo enlarger projects a negative onto photographic paper.
The steps repeat hundreds of times during fabrication, each time adding a new layer:
For decades, chip fabs used deep ultraviolet (DUV) light at 193 nm wavelength. As transistors shrank below 10nm, this wavelength became too large — imagine trying to paint a 2 nm feature with a brush 80 times wider. The industry's answer was Extreme Ultraviolet (EUV) at 13.5 nm — about 14× shorter wavelength, enabling 14× finer features.
Only one company on Earth makes EUV machines: ASML, based in the Netherlands. Each machine costs over $150 million, weighs 180 tonnes, contains over 100,000 components, and requires a 747 cargo plane to ship. TSMC has over 200 of them.
After the wafer is prepared, the first half of fabrication is FEOL (Front-End of Line) — actually constructing the transistors. Modern chips use FinFET (from 22nm to 5nm) or the newer GAAFET/nanosheet design (3nm and below).
Once transistors exist, they need to be connected. That's BEOL (Back-End of Line): building the metal interconnect stack — the highways that carry electrons between billions of transistors.
TSMC's N3 process uses 14+ metal layers of copper wiring, each layer separated by a dielectric (insulating) material. The lowest layers have the finest, densest wires (connecting nearby transistors). Higher layers have thicker wires for carrying power and longer signals.
Each "node" is a generation of fab process. The number (5nm, 3nm) no longer maps directly to a physical dimension — it's a marketing label for a combination of transistor density, performance, and power improvements.
| Node | Key technology | Transistor density | vs previous |
|---|---|---|---|
| 28nm | Planar MOSFET, DUV | ~26 MTr/mm² | baseline |
| 16nm | FinFET introduced | ~60 MTr/mm² | ~2.3× |
| 7nm | EUV (partial), 2nd-gen FinFET | ~91 MTr/mm² | ~1.5× |
| 5nm | Full EUV, dense FinFET | ~173 MTr/mm² | ~1.9× |
| 3nm | FinFlex (multi-fin), EUV | ~292 MTr/mm² | ~1.7× |
| 2nm | GAAFET / nanosheet, EUV | ~380+ MTr/mm² | ~1.3× |
After all fab steps are done, the wafer goes through wafer-level testing: robotic probe cards touch every chip on the wafer simultaneously, running electrical tests. Chips that fail are marked with a dot of ink.
The wafer is then diced — a diamond saw or laser cuts along the streets (gaps between chips) to separate individual dies. Good dies move to packaging; failed dies are discarded. The ratio of working dies to total dies is the yield — one of TSMC's most guarded secrets.
Finally, packaging. The die is attached to a substrate, flip-chip bonded (bumps of solder connect the die face-down to the substrate), and sealed. Advanced packaging like CoWoS (Chip-on-Wafer-on-Substrate) — used in NVIDIA's H100/H200 GPUs — stacks dies and HBM memory side-by-side on an interposer for massive bandwidth.
Every constraint you face in RTL design — maximum clock frequency, power budgets, wire routing rules, metal layer assignments — flows directly from this fab process. When a synthesis tool says "critical path is 1.2ns at 5nm," it's because the transistor switching speed and wire resistance of TSMC N5 set that limit. Understanding the fab process makes you a better hardware engineer.
Sand (SiO₂) is purified to 9N silicon, grown into a single crystal ingot, sliced into wafers, then patterned with photolithography hundreds of times to build transistors and metal interconnects.
Extreme Ultraviolet light at 13.5nm wavelength — 14× shorter than DUV. Enables sub-7nm features. Only ASML makes EUV machines ($150M+ each). TSMC has 200+.
A 3D transistor with a vertical silicon fin as the channel and a gate wrapping 3 sides — far better leakage control than flat planar transistors. Used from 22nm to 5nm.
FEOL (Front-End of Line) builds the transistors. BEOL (Back-End of Line) adds 14+ metal layers of copper wiring to connect them.
3–4 months of fab time (1,000+ steps), plus a few more weeks for packaging and testing.
N2 (2nm) is in production as of 2025–2026, using GAAFET (nanosheet) transistors. A16 (1.6nm) is in development.