Question 1

What is logic synthesis in VLSI?

Accepted Answer

Logic synthesis translates an RTL description (Verilog/VHDL) into a technology-mapped gate-level netlist using a standard cell library. The synthesizer reads RTL + timing constraints (SDC), applies Boolean optimization and technology mapping, and outputs a gate netlist and timing/area/power reports.

Question 2

What is the synthesis flow in ASIC design?

Accepted Answer

ASIC synthesis flow: (1) Read RTL — parse Verilog/VHDL; (2) Elaborate — build hierarchy, resolve parameters; (3) Constrain — apply SDC (create_clock, set_input_delay, set_output_delay, set_max_fanout); (4) Compile — generic logic optimization (GTECH) → technology mapping → incremental optimization; (5) Report — check timing (WNS/TNS), area, power; (6) Write out — netlist.v + SDC + SDF for P&R.

Question 3

What are SDC timing constraints?

Accepted Answer

SDC (Synopsys Design Constraints) defines timing requirements: create_clock sets the clock period; set_input_delay and set_output_delay define arrival and required times at ports; set_max_fanout and set_max_transition control physical limits; set_false_path and set_multicycle_path override default timing arcs; set_dont_touch prevents the tool from modifying critical cells.

Question 4

What is technology mapping in synthesis?

Accepted Answer

Technology mapping converts a generic Boolean network (NAND/NOR/INV) into cells from a foundry standard cell library (e.g., NAND2X1, DFF_Q, AOI22). The mapper selects cells that meet timing while minimizing area/power, using pattern matching or dynamic programming over the NAND graph. Cell sizing (drive strength) is then adjusted to meet slew and fanout constraints.

Logic Synthesis