VLSI Design Flow

Logic Synthesis

Transform RTL Verilog into a technology-mapped gate-level netlist — with timing constraints, logic optimization, and tapeout-ready outputs for place & route.

RTL (Verilog) → Elaborate → Constrain (SDC) → Compile → Optimize → Gate Netlist
RTL Input Verilog / VHDL Elaborate Hierarchy + Params Constrain SDC (clocks, delays) Compile Map + Optimize Gate Netlist + SDF + SDC SDC file + Liberty (.lib) ↓ Timing / Area / Power Reports Logic Synthesis Flow — RTL → Gate-Level Netlist
Synthesis translates RTL through elaboration, SDC constraint application, and technology mapping into a gate-level netlist ready for place & route.
Synthesis Topics
Core Concepts & Deep Dives
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Step 1
RTL to Gate-Level Netlist
How the synthesizer reads Verilog, elaborates hierarchy, builds a generic GTECH network, and maps it to library cells. NAND/NOR decomposition, don't-care optimization, and compile strategies.
GTECHBoolean optHierarchyDesign Compiler
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⏱️
Step 2
SDC Timing Constraints
create_clock, set_input_delay, set_output_delay, set_max_fanout, set_false_path, set_multicycle_path — complete SDC reference with real-world examples and common mistakes.
create_clockinput_delayfalse_pathMCP
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📉
Step 3
Area, Power & Timing Optimization
compile_ultra vs compile strategies, retiming, constant propagation, clock gating insertion, leakage optimization, multi-Vt cell selection, and timing closure techniques.
compile_ultraretimingmulti-Vtclock gating
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🗺️
Step 4
Technology Mapping
How the mapper selects standard cells from a Liberty library (.lib), cell sizing (drive strength), fanout-driven upsizing, and wire-load models vs actual extracted parasitics.
Liberty .libcell sizingfanoutwire-load model
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Industry Tools
Synthesis Tool Quick Reference
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Synopsys
Design Compiler (DC)
Industry-standard synthesis tool. Key commands: read_verilog, elaborate, link_library, source sdc, compile_ultra, write_verilog, write_sdf.
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Cadence
Genus Synthesis Solution
Cadence's synthesis engine with machine-learning-driven optimization. Key commands: read_hdl, elaborate, init_design, syn_gen, syn_map, syn_opt, write_hdl.
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Open-Source
Yosys Synthesis Suite
Open-source RTL synthesis for FPGA and ASIC flows. Key commands: read_verilog, synth, abc, techmap, write_verilog. Used in OpenROAD, SKY130 PDK flows.
Key Metrics at Synthesis
WNS
Worst Negative Slack — most critical timing path must be ≥ 0 ps at tapeout
TNS
Total Negative Slack — sum of all negative slacks; target 0 ps
Area
Total cell area (µm²) — combo + sequential + buffer/inverter cells
Power
Dynamic (switching) + static (leakage) — in µW or mW from report_power

Logic Synthesis — Turning RTL into Gates

Logic synthesis is the automated step that translates human-written RTL (Verilog or VHDL) into an optimised network of real logic gates from a target technology library. It is the hinge between design intent and physical implementation: you describe what the hardware should do, and the synthesis tool works out how to build it efficiently in silicon.

A synthesis tool performs three broad jobs. It elaborates the RTL into a generic logic representation, optimises that logic for your goals, and maps it onto the standard cells of a specific foundry library. Throughout, it is steered by constraints — clock definitions, input/output delays and timing exceptions written in SDC — that tell it how fast the design must run.

What synthesis decides

The result, a gate-level netlist, is what flows into physical design. Quality of results here sets the ceiling for the whole project: clean, well-constrained RTL synthesises into a fast, small, low-power design, while sloppy RTL or weak constraints create problems no downstream tool can fully fix. Try writing and compiling RTL in our online Verilog simulator to see the input side of this process.