What is Physical Design?
The RTL to GDSII Journey

Physical design is the stage of ASIC development where a gate-level netlist is transformed into a physical layout that a semiconductor foundry can manufacture. It is where the abstract logic becomes real transistors, wires, and masks — and one of the highest-demand, highest-paying disciplines in the semiconductor industry.

Where Does Physical Design Fit in the ASIC Flow?

The chip design flow has three major phases. Physical design occupies the entire backend — everything after logic synthesis and before the chip goes to the fab.

The Physical Design Flow Step by Step

Every ASIC physical design engagement follows the same sequence. The 15 days of this course teach each stage in depth — here is the full picture first:

Inputs to Physical Design

Outputs of Physical Design

Key Tools in the Industry

What Does a Physical Design Engineer Actually Do?

On a typical project, a senior PD engineer does a mix of:

• Floorplan and power planning — deciding where macros go, planning the power mesh to avoid IR drop violations under dynamic switching
• Timing closure — iterating on placement and ECO to close setup and hold violations across all PVT corners
• DRC debugging — resolving design-rule violations that occur during routing at advanced nodes
• Tcl script development — most PD work is scripted. You write scripts to automate runs, parse reports, apply ECOs, check status.
• Sign-off co-ordination — liaising with the STA, IR drop, DFT, and LEC teams to converge on a tapeout-ready database
• Technology decisions — at advanced nodes (7nm, 5nm, 3nm), selecting standard cell height, double-patterning colour assignment, FinFET orientation

Starting an Innovus Session: Your First Commands

Physical design is almost entirely command-line driven in production environments. Here is what a typical Innovus design import looks like:

# ── Load design ───────────────────────────────────────────
set_db init_design_netlist         ../netlist/top.v
set_db init_mmmc_file              ./mmmc.tcl
set_db init_lef_file               {tech.lef cells.lef macros.lef}

init_design

# ── Verify design loaded correctly ────────────────────────
get_db designs .name           ;# returns your top module name
get_db [get_db designs .] .insts   ;# list all instances

The mmmc.tcl file defines your Multi-Corner Multi-Mode (MCMM) analysis views — the PVT corners and operating modes the tool will analyse. You will learn MCMM in detail on Day 6.

# Define library sets per PVT corner
create_library_set -name libs_ss_125c \
    -timing [list ../lib/cells_ss_125c.lib ../lib/macros_ss_125c.lib]

create_library_set -name libs_ff_m40c \
    -timing [list ../lib/cells_ff_m40c.lib ../lib/macros_ff_m40c.lib]

# Define constraint modes (operating modes)
create_constraint_mode -name func_mode \
    -sdc_files {../sdc/top_func.sdc}

# Define delay corners (PVT + RC)
create_delay_corner -name ss_125c \
    -library_set libs_ss_125c \
    -rc_corner rc_worst

create_delay_corner -name ff_m40c \
    -library_set libs_ff_m40c \
    -rc_corner rc_best

# Combine into analysis views
create_analysis_view -name func_ss_setup \
    -constraint_mode func_mode -delay_corner ss_125c

create_analysis_view -name func_ff_hold \
    -constraint_mode func_mode -delay_corner ff_m40c

# Activate
set_analysis_view -setup {func_ss_setup} -hold {func_ff_hold}

Node Technology: What Changes at Each Node

Why Physical Design Skills Are So Valuable

Frequently Asked Questions