▶ Why Floorplanning Decides the Fate of Your Chip
- A bad floorplan causes routing congestion that no tool can fix later — the chip must be re-floorplanned
- Wrong utilization (e.g. 90%) → tools cannot route signal wires → timing closure impossible
- Poor macro placement → long clock paths between memories and logic → setup violations
- Missing power straps → IR drop hotspots → functional failures at speed
- Real: Apple A-series chip floorplans take weeks with 10+ engineers — it's that critical
1. What Is Floorplanning?
Floorplanning is the first step of physical design. It converts the gate-level netlist into a physical chip layout skeleton by defining:
- Die/core area and aspect ratio
- IO pad ring placement
- Hard macro (memory, IP) positions
- Power distribution network
- Partition and blockage regions
2. Die Size and Utilization
Utilization = (Total Std Cell Area) / (Core Area) × 100%
| Utilization % | Effect | Typical Use |
|---|---|---|
| < 50% | Large die, lots of whitespace, easy routing | Prototype / cost-insensitive designs |
| 60–70% | Good balance of area vs routability | Standard ASIC designs |
| 70–75% | Industry sweet spot | Most production chips |
| 80–85% | Tight routing, congestion risk | High-density, advanced nodes |
| > 90% | Very high congestion, likely unroutable | Avoid — ECO nightmare |
Core Area = Std Cell Area / Target Utilization
Die Area = Core Area + IO ring area + Pad ring width
Aspect Ratio = Die Height / Die Width (typically 0.9 – 1.1 for square die)
Die Area = Core Area + IO ring area + Pad ring width
Aspect Ratio = Die Height / Die Width (typically 0.9 – 1.1 for square die)
Example: Design has 500,000 std cells × avg 4 µm² = 2 mm² cell area. Target utilization = 70%. Core area = 2/0.70 = 2.857 mm². If square: core = 1.69 mm × 1.69 mm. Add IO ring ~150 µm → die ≈ 1.99 × 1.99 mm.
3. IO Placement
IO pads sit between the die edge and core area forming the IO ring. Each pad is a large driver cell that connects the chip's internal signals to package bumps or bond wires.
| IO Type | Purpose | Placement Consideration |
|---|---|---|
| Signal IO | Data, address, control signals | Place near the logic they connect to (minimize long wires) |
| Clock IO | External clock input | Place close to PLL/clock mux to minimize skew |
| Power/Ground IO | VDD/VSS supply | Distribute evenly, place near high-current blocks |
| Analog IO | ADC/DAC, reference pins | Isolate from digital noise, special ESD rules |
Industry Rule: Power IO pads should be evenly distributed around all 4 sides of the die — not clustered — to ensure uniform current delivery and minimize voltage drop across the die.
4. Macro Placement
Hard macros are pre-designed blocks with fixed layouts: SRAMs, ROMs, PLLs, PHY IPs, ADC/DAC blocks. They must be placed before standard cells.
Rules for Macro Placement
| Rule | Reason |
|---|---|
| Place macros against die edges or abutting each other | Avoids routing channels being cut in the middle of the core |
| Leave halo/margin (~5–10 µm) around macros | Routing channels for signal wires to access macro pins |
| Align macro orientation with power strap direction | Macro power pins should connect easily to straps above |
| Place memory near the logic that uses it | Reduces wire length → better timing and lower power |
| Keep analog macros (PLL, ADC) away from noisy digital logic | Substrate noise coupling causes PLL jitter, ADC errors |
Common Mistake: Placing macros in the center of the die creates routing channels on all 4 sides that block standard cell routing. Always push macros to corners or edges — this is called "push macro to corner" strategy.
5. Power Planning
Power planning creates the Power Distribution Network (PDN) — the grid of metal wires that deliver VDD and VSS to every cell in the design.
| PDN Layer | Metal Layer | Purpose |
|---|---|---|
| Power Rings | Top metals (M8–M9) | Surround core and macros, carry bulk current from pads |
| Power Straps | M5–M7 (H and V) | Distribute current across entire die, low impedance grid |
| Cell Rails | M1 | Horizontal VDD/VSS rails inside each standard cell row |
| Vias | All via layers | Connect strap layers to rails — via stacks used for low R |
6. Blockages
| Blockage Type | Blocks | Use Case |
|---|---|---|
| Placement Blockage | Standard cell placement | Keep cells away from macro halos, IO area, decap rows |
| Routing Blockage | Signal routing on specified layers | Protect analog areas, keep RF signals away from digital |
| Hard Blockage | Both placement and routing | Inside hard macros — nothing can be placed or routed there |
| Soft Blockage | Placement only, routing allowed | Guides placement to avoid congested zones |
| Halo | Placement around macros | Auto-created margin around hard macros for routing channels |
Interview Questions — Floorplanning
What is the ideal utilization for a standard ASIC design, and what happens if it is too high?
Ideal utilization: 70–75%
If utilization is too high (>85%):
• Routing congestion — insufficient whitespace for signal wires
• Tool cannot achieve timing closure — setup/hold violations remain
• ECO (Engineering Change Order) implementation becomes very difficult
• Fixing DRC violations becomes nearly impossible
If too low (<50%): die area is larger → higher cost per wafer → poor PPA (Power, Performance, Area).
If utilization is too high (>85%):
• Routing congestion — insufficient whitespace for signal wires
• Tool cannot achieve timing closure — setup/hold violations remain
• ECO (Engineering Change Order) implementation becomes very difficult
• Fixing DRC violations becomes nearly impossible
If too low (<50%): die area is larger → higher cost per wafer → poor PPA (Power, Performance, Area).
Why should macros be placed at the corners/edges of the chip rather than in the center?
Macros at edges → better routability
• Macros in center split the routing area into 4 disconnected channels → severe congestion
• Macros at edges/corners leave one large contiguous routing area for standard cells
• Reduces the number of routing detours needed
• Makes power strap connections simpler — straps run uninterrupted
• Reduces clock tree buffer count since macros don't obstruct clock routing
Exception: some large blocks may need to be centered for symmetry (e.g., analog blocks surrounded by equally spaced digital logic).
• Macros in center split the routing area into 4 disconnected channels → severe congestion
• Macros at edges/corners leave one large contiguous routing area for standard cells
• Reduces the number of routing detours needed
• Makes power strap connections simpler — straps run uninterrupted
• Reduces clock tree buffer count since macros don't obstruct clock routing
Exception: some large blocks may need to be centered for symmetry (e.g., analog blocks surrounded by equally spaced digital logic).
What is IR drop and how does floorplanning help reduce it?
IR drop = voltage drop across power network resistance
V_drop = I × R_PDN. If VDD = 1.0V and IR drop = 150 mV, cells at that point see only 0.85V → slower switching → setup violations.
Floorplanning reduces IR drop by:
• Adding wider power straps (lower R) in the PDN
• Adding more power IO pads near high-current blocks
• Placing high-current macros (e.g., CPU core) near power IO pads
• Adding decoupling capacitors (decap cells) near sensitive logic
• Using via stacking for lower vertical resistance
Target: IR drop < 10% of VDD (e.g., <100 mV for 1.0V supply).
V_drop = I × R_PDN. If VDD = 1.0V and IR drop = 150 mV, cells at that point see only 0.85V → slower switching → setup violations.
Floorplanning reduces IR drop by:
• Adding wider power straps (lower R) in the PDN
• Adding more power IO pads near high-current blocks
• Placing high-current macros (e.g., CPU core) near power IO pads
• Adding decoupling capacitors (decap cells) near sensitive logic
• Using via stacking for lower vertical resistance
Target: IR drop < 10% of VDD (e.g., <100 mV for 1.0V supply).
What is the difference between a hard macro and a soft macro?
Hard Macro: Fixed pre-characterized layout block — shape, size, and pin positions are fixed. Examples: SRAM compilers, PHY IPs, PLLs, ADC/DAC. Cannot be resized or modified. Must be placed as-is.
Soft Macro: A block described at RTL/gate level that can be synthesized and placed like standard cells. Shape and size are flexible — the PnR tool decides placement. Examples: a DSP block described in Verilog, a FIFO IP delivered as RTL.
Firm Macro: A macro with a fixed netlist but flexible physical implementation — area is estimated but exact shape can change slightly. Between hard and soft.
Soft Macro: A block described at RTL/gate level that can be synthesized and placed like standard cells. Shape and size are flexible — the PnR tool decides placement. Examples: a DSP block described in Verilog, a FIFO IP delivered as RTL.
Firm Macro: A macro with a fixed netlist but flexible physical implementation — area is estimated but exact shape can change slightly. Between hard and soft.
Name key Innovus commands used in floorplanning.
Cadence Innovus floorplan commands:
floorPlan -coreMarginsBy die -site core -aspectRatio 1.0 -coreUtilization 0.70 — set die size and utilizationaddRing -nets {VDD VSS} -layer {top M8 bottom M8 left M8 right M8} -width 10 — add power ringsaddStripe -nets {VDD VSS} -layer M7 -direction vertical -width 4 -spacing 0.5 -set_to_set_distance 40 — add power strapsplaceInstance SRAM_inst 100 200 R0 — place macro at coordinatescreatePlacementBlockage -box {x1 y1 x2 y2} -type hard — create blockagesaveDesign floorplan.enc — save state
What is a decoupling capacitor (decap) cell and why is it added during floorplanning?
Decap cell: A standard cell filled with NMOS/PMOS transistors wired as capacitors between VDD and VSS. Acts as a local charge reservoir.
Why needed: When many cells switch simultaneously (e.g., clock edge), they demand a sudden burst of current. The PDN resistance/inductance can't supply this instantly → voltage droop (dynamic IR drop).
Decap cells store charge locally and release it instantly when needed — smoothing out the voltage droop.
Placement: Added in spare whitespace between macros and in cell rows near high-switching regions (e.g., near clock buffers, bus interfaces). Typically 5–15% of core area is decap cells.
Why needed: When many cells switch simultaneously (e.g., clock edge), they demand a sudden burst of current. The PDN resistance/inductance can't supply this instantly → voltage droop (dynamic IR drop).
Decap cells store charge locally and release it instantly when needed — smoothing out the voltage droop.
Placement: Added in spare whitespace between macros and in cell rows near high-switching regions (e.g., near clock buffers, bus interfaces). Typically 5–15% of core area is decap cells.