1. What is Placement?
After floorplanning establishes the die outline, IO ring, macro positions, and power grid, placement determines where each standard cell (AND gates, flip-flops, MUXes, buffers) will physically sit within the core area.
Input: Synthesized netlist (gate-level) + DEF with floorplan (macro locations, power grid, blockages)
Output: DEF with XY coordinates for every standard cell
Constraint: Timing constraints from SDC, target utilization from floorplan
Output: DEF with XY coordinates for every standard cell
Constraint: Timing constraints from SDC, target utilization from floorplan
Global Placement
→
Legalization
→
Detailed Placement
→
Placement Optimization
2. Global Placement
Global placement spreads all cells across the core area by minimizing a cost function — typically a combination of half-perimeter wire length (HPWL), timing slack, and congestion density. At this stage cells may overlap; the placer treats each cell as a continuous variable position.
Cost Function Minimized
Cost = w₁ × HPWL + w₂ × TimingPenalty + w₃ × CongestionPenalty
HPWL (Half-Perimeter Wire Length) = ½ × (Δx + Δy) of the bounding box of each net. Minimizing HPWL reduces estimated wire length, which reduces delay, power, and routing congestion.
Global Placement Algorithms
| Algorithm | Approach | Used In |
|---|---|---|
| Force-Directed | Cells connected by nets attract each other like springs; cells repel when they overlap | Academic tools, early commercial |
| ePlace / RePlAce | Electrostatics analogy — cells act as charges, density enforced by potential fields | OpenROAD |
| Simulated Annealing | Iterative random moves accepted with decreasing probability; global optimum search | Earlier Synopsys tools |
| Analytical (gradient) | Non-linear optimization of cost function using conjugate gradient methods | Innovus, ICC2 internal |
Key insight: Global placement determines the overall topology — which cells end up near each other. This directly impacts wirelength and congestion. A poor global placement cannot be fully fixed by detailed placement.
3. Legalization
After global placement, cells may overlap and sit off-grid. Legalization moves each cell to a legal position: on the placement grid (row-height aligned), no overlaps, within permitted regions, correct flip orientation (N/FS for alternating rows).
Legality Rules
| Rule | Requirement | Violation Impact |
|---|---|---|
| Row alignment | Cell origin Y must snap to row boundary | Power rail shorts, VDD/VSS mismatch |
| Grid alignment | Cell origin X must be on placement grid (typically 0.2µm or site width) | DRC violations after routing |
| No overlap | No two cells may share any area | Physical impossibility — tool error |
| Flip orientation | Adjacent rows flip VDD/VSS rails (N-row, FS-row alternating) | Power short between adjacent rows |
| Blockage respect | No cell inside a placement blockage | Congestion, DRC, functional error |
| Fence regions | Cells in a module group must stay in their fence | Partition violation, functional error |
Legalization Algorithms
Abacus Algorithm
For each cell, tries to place it at its global position; if blocked, slides along the row. Minimizes total displacement. Most widely used in commercial tools (Innovus, ICC2 internally).
Tetris Algorithm
Places cells one by one into the leftmost available legal position in the row closest to the global position. Fast but higher displacement than Abacus.
Legalization displacement (how far cells move from global positions) is a key quality metric. High displacement degrades timing because cells end up far from where the global placer intended for timing optimization.
4. Detailed Placement
Detailed placement performs local optimizations on the legalized placement to improve timing and reduce wirelength without moving cells far. Operations are confined to small windows of adjacent cells.
Detailed Placement Operations
| Operation | What It Does | Goal |
|---|---|---|
| Cell swapping | Exchange positions of two logically equivalent cells | Reduce wire length or improve timing |
| Cell sliding | Slide a cell left/right within its row | Reduce wire length, fix hold |
| Cell mirroring | Flip cell horizontally to use a closer pin | Reduce net length |
| Reordering | Reorder cells within a row segment | Reduce crossing wires |
| Global swap | Swap cells across different rows/regions | Fix congestion hotspots |
Innovus command:
refine_placement -effort medium — runs detailed placement optimization. check_place verifies legality afterward.
5. Timing-Driven Placement
Timing-driven placement (TDP) assigns higher priority to placing cells on critical paths close together — minimizing the wire delay on paths with small slack. Non-critical paths are placed with less constraint to improve overall density.
Timing-Driven Placement Metrics
| Metric | Definition | Target |
|---|---|---|
| WNS | Worst Negative Slack — most negative timing path | WNS ≥ 0 (or within budget for post-route fix) |
| TNS | Total Negative Slack — sum of all negative slacks | TNS = 0 (no violations) |
| NVP | Number of Violating Paths | 0 |
| HPWL | Half-Perimeter Wire Length (estimated routing) | Minimize |
| Congestion | Routing demand vs capacity ratio per tile | <1.0 (no overflow) |
Real-World Placement Guidelines
- Run pre-placement timing to know critical paths before placing
- Set placement effort to high for first iteration (catches more issues)
- Check placement congestion map — hotspots will fail routing later
- Target WNS < −200ps at placement (post-route optimization will fix up to 200ps)
- TNS > −5ns at placement is usually a red flag for the current floorplan
- Use
report_congestionafter placement — GRC overflow > 5% needs floorplan fix - Placement blockages near macros reduce congestion around hard IP boundaries
6. Congestion-Driven Placement
Congestion occurs when too many nets need to cross a small routing tile — more wires than the metal tracks can accommodate. Congestion at placement predicts routing hotspots and DRC failures.
Congestion Metrics
Congestion Ratio = Routing Demand / Routing Capacity
Ratio >1.0 means overflow — routing will fail in that tile. Commercial tools report this as a heat map where red = severe overflow.
Congestion Reduction Techniques
| Technique | How It Helps |
|---|---|
| Lower utilization | Give cells more space → fewer wires crossing any tile |
| Spread macros | Avoid macro clusters that force logic to route around them |
| Add placement blockages | Keep cells away from macro halos and congested corners |
| Spread high-fanout nets | High-fanout drivers with many sinks create convergence congestion |
| Partial floorplan re-do | If hotspot is macro-related, move the macro to a different corner |
| Add routing layers | If available — more metal tracks increase capacity |
Rule of thumb: If congestion overflow >5% after global routing, revisit the floorplan. If overflow is 1–5%, detailed placement and routing optimizations can usually resolve it.
7. Placement Commands — Innovus & ICC2
| Tool | Command | Purpose |
|---|---|---|
| Innovus | place_design | Run full placement (global + legalize + detailed) |
| Innovus | place_design -effort high | Higher effort for better QoR (slower) |
| Innovus | refine_placement | Detailed placement optimization (post-place) |
| Innovus | check_place | Verify legality (no overlaps, row alignment) |
| Innovus | report_timing -max_paths 50 | Post-placement timing report |
| Innovus | report_congestion | Show GRC overflow heatmap |
| ICC2 | create_placement | Run global placement |
| ICC2 | place.legalize | Legalize current placement |
| ICC2 | refine_opt | Post-placement optimization |
| OpenROAD | global_placement | RePlAce global placement |
| OpenROAD | detailed_placement | OpenDP detailed placement + legalization |
8. Interview Questions & Answers
What is the difference between global placement and detailed placement?
Global placement assigns approximate coordinates to minimize a cost function (HPWL + timing + congestion). Cells may overlap at this stage — the placer treats positions as continuous variables. Detailed placement takes the global positions, legalizes them (snaps to grid, removes overlaps, respects row orientation), then performs local optimizations (swapping, sliding) to improve timing and wirelength. Global sets the topology; detailed refines it legally.
What is legalization and why is it needed after global placement?
Global placement uses continuous optimization — cells can sit at any floating-point XY position and overlap. Legalization moves cells to the nearest legal positions: (1) snap X to placement grid (site width, typically 0.2µm), (2) snap Y to row boundaries, (3) remove all cell-to-cell overlaps, (4) match row orientation (N / FS alternating rows), (5) respect placement blockages. Without legalization, the placement cannot be physically manufactured and routing would fail.
What is WNS and TNS and what are typical targets at placement stage?
WNS (Worst Negative Slack) = the most negative timing path slack. If WNS = −300ps, the worst path is 300ps late. TNS (Total Negative Slack) = sum of all negative slacks across all violating paths — measures overall severity of timing violations.
Targets at placement: Post-place routing adds ~100–300ps of wire delay. So at placement, targeting WNS ≥ −200ps (setup) gives enough margin for routing to still converge. TNS should be less than −5ns; high TNS at placement usually means the floorplan or synthesis has a fundamental issue that placement cannot fix.
Targets at placement: Post-place routing adds ~100–300ps of wire delay. So at placement, targeting WNS ≥ −200ps (setup) gives enough margin for routing to still converge. TNS should be less than −5ns; high TNS at placement usually means the floorplan or synthesis has a fundamental issue that placement cannot fix.
How do you identify and resolve placement congestion?
Identify: Run
Resolve: (1) Reduce utilization (more room for routing). (2) Move macros away from congestion corners. (3) Add placement blockages near macro halos to force cells away. (4) Spread high-fanout nets (buffer insertion during placement). (5) If systemic, revisit floorplan — move large macros to different corners. (6) Use routing layer promotions if available. Target overflow <1% before proceeding to CTS.
report_congestion (Innovus) or check the congestion heatmap. Look for GRC (Global Route Congestion) overflow >1.0 in any tile — red tiles on the heatmap indicate routing will fail there.Resolve: (1) Reduce utilization (more room for routing). (2) Move macros away from congestion corners. (3) Add placement blockages near macro halos to force cells away. (4) Spread high-fanout nets (buffer insertion during placement). (5) If systemic, revisit floorplan — move large macros to different corners. (6) Use routing layer promotions if available. Target overflow <1% before proceeding to CTS.
Why is timing-driven placement important? How does it differ from wire-length-driven placement?
Wire-length-driven placement minimizes total HPWL equally for all nets — treats all nets as equally important. Timing-driven placement weights critical-path nets higher: it places cells on the most timing-critical paths as close together as possible to minimize wire delay, even if this slightly increases total wirelength.
Importance: Wire delay = RC delay ∝ wire length. A 500µm wire at 5GHz can contribute 50–100ps delay, which may be the entire timing budget on a critical path. Timing-driven placement ensures critical paths get short wires, while non-critical paths can absorb longer routes without violating timing.
Importance: Wire delay = RC delay ∝ wire length. A 500µm wire at 5GHz can contribute 50–100ps delay, which may be the entire timing budget on a critical path. Timing-driven placement ensures critical paths get short wires, while non-critical paths can absorb longer routes without violating timing.
What are filler cells and why are they inserted after placement?
Filler cells (or fill cells) are dummy standard cells with no logic function — they contain only N-well, P-well, and substrate connections. They are inserted into gaps between standard cells after placement to: (1) maintain N-well and P-well continuity across the row (required for proper implant mask), (2) complete VDD/VSS rail connectivity through the row, (3) satisfy design rules for well-tap spacing (prevent latch-up), (4) provide a uniform substrate for OPC and lithographic correctness. Without fillers, gaps in rows cause DRC violations during sign-off.