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Part of Curriculum: Protocol RTL Design (Module 6: APB Master Transaction Controller)
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Level 6 Advanced ★ Advanced #42 50 pts ✓ Solved

AMBA APB Master State Machine Controller

Advanced RTL & Protocol Design · advanced-rtl, apb-protocol, systemverilog, asic, fpga

Design a synthesizable AMBA APB master finite state machine that accepts internal core commands and drives standard APB bus transactions.

Module Specification
Write a synthesizable Verilog module named top_module matching the ports below exactly.
📐 Circuit Schematic Diagram
reqreq_writereq_addr[7:0]req_wdata[31:0]readyrdata[31:0]err>clkrst_nAMBA APB MASTER STATPROTOCOL INTERFACE
⚡ Timing & Synthesizability Constraints

Timing Contract: Clocked on rising edge of clk with active-low synchronous reset rst_n. Master must assert PSEL during SETUP and add PENABLE in ACCESS, holding PADDR/PWDATA stable until PREADY=1.

RTL Constraints: Synthesizable Verilog-2001. No # delays. Clean Moore/Mealy FSM implementation.

Objective: Implement an APB Master Controller converting internal single-cycle request pulses into 2-phase APB transactions (SETUP -> ACCESS). Support slave wait states via PREADY, capture PRDATA on read completion, and support back-to-back requests.

Prerequisites: Finite state machines, AMBA 3 APB master timing, handshaking protocols.
Port Contract
PortDirWidthDescription
clk, rst_ninput1Clock and active-low synchronous reset
reqinput1Internal transfer trigger
req_writeinput11 = Write, 0 = Read
req_addr[7:0]input8Requested memory address
req_wdata[31:0]input32Requested write data
readyoutput1High when master is idle and can accept requests
rdata[31:0]output32Captured read data valid when ready pulses high
erroutput1Asserted if slave returned PSLVERR=1
PSEL, PENABLE, PWRITEoutput1APB control signals
PADDR[7:0], PWDATA[31:0]output8, 32APB address and write data lines
PRDATA[31:0], PREADY, PSLVERRinput32, 1, 1APB slave feedback signals
Expected Waveform (Golden Timing Contract)
💡 Need Guidance? Progressive Hints (3 Levels)
Hint 1: Conceptual Direction & Hardware Primitives
Use a 2-bit state register: IDLE (00), SETUP (01), ACCESS (10).
Hint 2: Implementation Architecture & Approach
When in IDLE and req=1, latch req_addr and req_wdata, assert PSEL=1 and PENABLE=0, and move to SETUP.
Hint 3: Edge Cases, Timing & Verilog Syntax
In ACCESS, hold PADDR and PWDATA perfectly constant. Only move back to IDLE (or SETUP for back-to-back) once PREADY is sampled high.
🔒 Reveal Verified Reference RTL Solution (Click to expand)
⚠️ Self-Discovery Warning: Try solving and simulating first! Viewing the verified reference implementation will bypass the real debugging experience.
Verified Synthesizable RTL 
module top_module (
  input  wire        clk,
  input  wire        rst_n,
  input  wire        req,
  input  wire        req_write,
  input  wire [7:0]  req_addr,
  input  wire [31:0] req_wdata,
  output reg         ready,
  output reg  [31:0] rdata,
  output reg         err,
  output reg         PSEL,
  output reg         PENABLE,
  output reg         PWRITE,
  output reg  [7:0]  PADDR,
  output reg  [31:0] PWDATA,
  input  wire [31:0] PRDATA,
  input  wire        PREADY,
  input  wire        PSLVERR
);

  localparam IDLE   = 2'b00;
  localparam SETUP  = 2'b01;
  localparam ACCESS = 2'b10;

  reg [1:0] state;

  always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
      state   <= IDLE;
      ready   <= 1'b1;
      rdata   <= 32'h0;
      err     <= 1'b0;
      PSEL    <= 1'b0;
      PENABLE <= 1'b0;
      PWRITE  <= 1'b0;
      PADDR   <= 8'h0;
      PWDATA  <= 32'h0;
    end else begin
      case (state)
        IDLE: begin
          PENABLE <= 1'b0;
          if (req) begin
            state   <= SETUP;
            ready   <= 1'b0;
            PSEL    <= 1'b1;
            PWRITE  <= req_write;
            PADDR   <= req_addr;
            PWDATA  <= req_wdata;
            err     <= 1'b0;
          end else begin
            PSEL  <= 1'b0;
            ready <= 1'b1;
          end
        end

        SETUP: begin
          state   <= ACCESS;
          PENABLE <= 1'b1;
        end

        ACCESS: begin
          if (PREADY) begin
            err <= PSLVERR;
            if (!PWRITE) begin
              rdata <= PRDATA;
            end
            if (req) begin
              state   <= SETUP;
              PSEL    <= 1'b1;
              PENABLE <= 1'b0;
              PWRITE  <= req_write;
              PADDR   <= req_addr;
              PWDATA  <= req_wdata;
              ready   <= 1'b0;
            end else begin
              state   <= IDLE;
              PSEL    <= 1'b0;
              PENABLE <= 1'b0;
              ready   <= 1'b1;
            end
          end
        end

        default: state <= IDLE;
      endcase
    end
  end

endmodule
Verilog-2001 / SV Saved
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RTL Problems / Level 6 · Advanced RTL & Protocol Design

What You Will Learn

By solving AMBA APB Master State Machine Controller, you will acquire core industry skills:

  • Synthesizable hardware modeling in standard Verilog-2001 / SystemVerilog.
  • Correct handling of interface port contracts, edge-triggered clocks, and active-low/high resets.
  • Simulation waveform interpretation and debugging using timing diagrams (VCD traces).
  • Architectural avoidance of timing violations, glitching hazards, and synthesis warnings.

Problem Statement & Requirements

Design a synthesizable AMBA APB master finite state machine that accepts internal core commands and drives standard APB bus transactions.

Hardware design teams at leading semiconductor firms evaluate these exact port contracts, race-condition assertions, and corner cases during technical design reviews and ASIC engineer interviews.

Objective: Implement an APB Master Controller converting internal single-cycle request pulses into 2-phase APB transactions (SETUP -> ACCESS). Support slave wait states via PREADY, capture PRDATA on read completion, and support back-to-back requests.

Prerequisites: Finite state machines, AMBA 3 APB master timing, handshaking protocols.

Port List & Interface Timing

The hidden testbench instantiates top_module. Module port names and bit-widths must match the interface contract exactly:

PortDirWidthDescription
clk, rst_ninput1Clock and active-low synchronous reset
reqinput1Internal transfer trigger
req_writeinput11 = Write, 0 = Read
req_addr[7:0]input8Requested memory address
req_wdata[31:0]input32Requested write data
readyoutput1High when master is idle and can accept requests
rdata[31:0]output32Captured read data valid when ready pulses high
erroutput1Asserted if slave returned PSLVERR=1
PSEL, PENABLE, PWRITEoutput1APB control signals
PADDR[7:0], PWDATA[31:0]output8, 32APB address and write data lines
PRDATA[31:0], PREADY, PSLVERRinput32, 1, 1APB slave feedback signals

Timing Constraints & Synthesizable RTL Rules

⚡ Synthesizable Implementation Guidelines

Timing Contract: Clocked on rising edge of clk with active-low synchronous reset rst_n. Master must assert PSEL during SETUP and add PENABLE in ACCESS, holding PADDR/PWDATA stable until PREADY=1.

Synthesis Constraints: Synthesizable Verilog-2001. No # delays. Clean Moore/Mealy FSM implementation.

Architectural Deep Dive & Implementation Walkthrough

APB Master Controller Architecture

An APB Master translates transaction requests from processor cores, DMA engines, or debug bridges into valid APB bus waveforms.

State Machine Execution

  1. IDLE: The master asserts ready = 1. When req = 1 is received, the master captures address, write-enable, and payload, asserts PSEL = 1, and enters SETUP.
  2. SETUP: PSEL = 1 and PENABLE = 0. Address and control signals are stable. The state machine transitions unconditionally to ACCESS on the next clock edge.
  3. ACCESS: The master asserts PENABLE = 1. If the slave asserts PREADY = 0, the master remains in ACCESS indefinitely without changing any control or data signals. Once PREADY = 1 is sampled, the transfer completes, read data is latched, and the master returns to IDLE (or restarts SETUP for back-to-back operations).

Common RTL Designer Pitfalls

⚠️ Common Mistakes to Avoid

Deasserting PENABLE or changing PADDR/PWDATA when PREADY=0. The APB specification strictly requires all signals to remain stable throughout wait states.

Silicon & Hardware Engineering Notes

🛠️ ASIC vs FPGA Hardware Considerations

APB masters in safety-critical SoCs (ISO 26262) incorporate a timeout counter in the ACCESS state to abort hung transactions if a peripheral never asserts PREADY.

Starter RTL Code

module top_module (
  input  wire        clk,
  input  wire        rst_n,
  input  wire        req,
  input  wire        req_write,
  input  wire [7:0]  req_addr,
  input  wire [31:0] req_wdata,
  output reg         ready,
  output reg  [31:0] rdata,
  output reg         err,
  output reg         PSEL,
  output reg         PENABLE,
  output reg         PWRITE,
  output reg  [7:0]  PADDR,
  output reg  [31:0] PWDATA,
  input  wire [31:0] PRDATA,
  input  wire        PREADY,
  input  wire        PSLVERR

Verified Reference Solution

🔒 Reveal Verified Reference RTL Solution
module top_module (
  input  wire        clk,
  input  wire        rst_n,
  input  wire        req,
  input  wire        req_write,
  input  wire [7:0]  req_addr,
  input  wire [31:0] req_wdata,
  output reg         ready,
  output reg  [31:0] rdata,
  output reg         err,
  output reg         PSEL,
  output reg         PENABLE,
  output reg         PWRITE,
  output reg  [7:0]  PADDR,
  output reg  [31:0] PWDATA,
  input  wire [31:0] PRDATA,
  input  wire        PREADY,
  input  wire        PSLVERR
);

  localparam IDLE   = 2'b00;
  localparam SETUP  = 2'b01;
  localparam ACCESS = 2'b10;

  reg [1:0] state;

  always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
      state   <= IDLE;
      ready   <= 1'b1;
      rdata   <= 32'h0;
      err     <= 1'b0;
      PSEL    <= 1'b0;
      PENABLE <= 1'b0;
      PWRITE  <= 1'b0;
      PADDR   <= 8'h0;
      PWDATA  <= 32'h0;
    end else begin
      case (state)
        IDLE: begin
          PENABLE <= 1'b0;
          if (req) begin
            state   <= SETUP;
            ready   <= 1'b0;
            PSEL    <= 1'b1;
            PWRITE  <= req_write;
            PADDR   <= req_addr;
            PWDATA  <= req_wdata;
            err     <= 1'b0;
          end else begin
            PSEL  <= 1'b0;
            ready <= 1'b1;
          end
        end

        SETUP: begin
          state   <= ACCESS;
          PENABLE <= 1'b1;
        end

        ACCESS: begin
          if (PREADY) begin
            err <= PSLVERR;
            if (!PWRITE) begin
              rdata <= PRDATA;
            end
            if (req) begin
              state   <= SETUP;
              PSEL    <= 1'b1;
              PENABLE <= 1'b0;
              PWRITE  <= req_write;
              PADDR   <= req_addr;
              PWDATA  <= req_wdata;
              ready   <= 1'b0;
            end else begin
              state   <= IDLE;
              PSEL    <= 1'b0;
              PENABLE <= 1'b0;
              ready   <= 1'b1;
            end
          end
        end

        default: state <= IDLE;
      endcase
    end
  end

endmodule

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Frequently Asked Questions

What does AMBA APB Master State Machine Controller require?

Design a synthesizable AMBA APB master finite state machine that accepts internal core commands and drives standard APB bus transactions. Implement it as Verilog module top_module matching the listed ports.

Is this design combinational or sequential?

Tags: advanced-rtl, apb-protocol, systemverilog, asic, fpga. If a clock signal is present in the port table, implement it as sequential logic; otherwise, use continuous assignments or combinational blocks.

How is my solution graded?

A hidden SystemVerilog testbench simulates your module in the cloud judge. You pass when all directed corner cases match the golden model and the VCD timing waveform matches the contract.

How does this challenge help with semiconductor interviews?

Technical interviewers at NVIDIA, Qualcomm, Apple, and Intel routinely ask candidates to code, debug, and explain the timing waveforms of AMBA APB Master State Machine Controller to assess real-world synthesizability and race-condition awareness.