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Part of Curriculum: Protocol RTL Design (Module 6: APB Master Transaction Controller)
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Level 6 Hard 50 pts ✓ Solved

APB Protocol Master FSM

RTL Protocol Design · protocols, apb, fsm, bus

Implement an AMBA APB Master state machine handling IDLE, SETUP, and ACCESS phases with PREADY wait states.

Module Specification
Write a synthesizable Verilog module named top_module matching the ports below exactly.
📐 Circuit Schematic Diagram
NEXT STATECOMBINATIONALSTATE REG[D-FF / CLK]OUTPUTLOGICstartpselcurrent_state [Feedback Loop]>clk, rst
⚡ Timing & Synthesizability Constraints

Timing Contract: Strict synchronous timing aligned to posedge clk or zero-delay combinational propagation.

RTL Constraints: Synthesizable Verilog-2001. No # delays in synthesizable RTL.

Concept: APB transfer cycle. SETUP phase asserts PSEL=1 with address and write flags; ACCESS phase asserts PENABLE=1 and waits until the slave returns PREADY=1 before completing.
Port Contract
NameDirWidthDescription
clkinput1System clock
rst_ninput1Active-low reset
startinput1Trigger new transaction
writeinput11=Write, 0=Read
addr_ininput32Target memory address
wdata_ininput32Write data payload
preadyinput1Slave ready handshake
prdatainput32Slave read data
pseloutput1Slave select
penableoutput1Transfer phase enable
pwriteoutput1Direction indicator
paddroutput32Address driven to bus
pwdataoutput32Write data driven to bus
rdata_outoutput32Captured read data
doneoutput1Strobe indicating transfer complete
Expected Waveform (Golden Timing Contract)
Verilog-2001 / SV Saved
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Simulation Timing Diagram (VCD Waveform)
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RTL Problems / Level 6 · RTL Protocol Design

What You Will Learn

By solving APB Protocol Master FSM, you will acquire core industry skills:

  • Synthesizable hardware modeling in standard Verilog-2001 / SystemVerilog.
  • Correct handling of interface port contracts, edge-triggered clocks, and active-low/high resets.
  • Simulation waveform interpretation and debugging using timing diagrams (VCD traces).
  • Architectural avoidance of timing violations, glitching hazards, and synthesis warnings.

Problem Statement & Requirements

Implement an AMBA APB Master state machine handling IDLE, SETUP, and ACCESS phases with PREADY wait states.

Hardware design teams at leading semiconductor firms evaluate these exact port contracts, race-condition assertions, and corner cases during technical design reviews and ASIC engineer interviews.

Concept: APB transfer cycle. SETUP phase asserts PSEL=1 with address and write flags; ACCESS phase asserts PENABLE=1 and waits until the slave returns PREADY=1 before completing.

Port List & Interface Timing

The hidden testbench instantiates top_module. Module port names and bit-widths must match the interface contract exactly:

NameDirWidthDescription
clkinput1System clock
rst_ninput1Active-low reset
startinput1Trigger new transaction
writeinput11=Write, 0=Read
addr_ininput32Target memory address
wdata_ininput32Write data payload
preadyinput1Slave ready handshake
prdatainput32Slave read data
pseloutput1Slave select
penableoutput1Transfer phase enable
pwriteoutput1Direction indicator
paddroutput32Address driven to bus
pwdataoutput32Write data driven to bus
rdata_outoutput32Captured read data
doneoutput1Strobe indicating transfer complete

Timing Constraints & Synthesizable RTL Rules

⚡ Synthesizable Implementation Guidelines

Timing Contract: Strict synchronous timing aligned to posedge clk or zero-delay combinational propagation.

Synthesis Constraints: Synthesizable Verilog-2001. No # delays in synthesizable RTL.

Starter RTL Code

module top_module (
  input  wire        clk,
  input  wire        rst_n,
  input  wire        start,
  input  wire        write,
  input  wire [31:0] addr_in,
  input  wire [31:0] wdata_in,
  input  wire        pready,
  input  wire [31:0] prdata,
  output reg         psel,
  output reg         penable,
  output reg         pwrite,
  output reg  [31:0] paddr,
  output reg  [31:0] pwdata,
  output reg  [31:0] rdata_out,
  output reg         done
);

Related RTL Problems in Level 6

  • Manchester Encoder — Combine a data bit with the clock to produce a Manchester-encoded line signal — the self-clocking encoding used in classic Ethernet and RFID.
  • Manchester Decoder — Recover the original data bit from a Manchester-encoded line signal — the exact inverse of the Manchester Encoder problem.
  • Quadrature Rotary Encoder Decoder — Decode the two-phase A/B signal from a real rotary knob or mouse wheel into a direction and position count — sample B on every rising edge of A.

Connected EcrioniX Learning Resources

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Frequently Asked Questions

What does APB Protocol Master FSM require?

Implement an AMBA APB Master state machine handling IDLE, SETUP, and ACCESS phases with PREADY wait states. Implement it as Verilog module top_module matching the listed ports.

Is this design combinational or sequential?

Tags: protocols, apb, fsm, bus. If a clock signal is present in the port table, implement it as sequential logic; otherwise, use continuous assignments or combinational blocks.

How is my solution graded?

A hidden SystemVerilog testbench simulates your module in the cloud judge. You pass when all directed corner cases match the golden model and the VCD timing waveform matches the contract.

How does this challenge help with semiconductor interviews?

Technical interviewers at NVIDIA, Qualcomm, Apple, and Intel routinely ask candidates to code, debug, and explain the timing waveforms of APB Protocol Master FSM to assess real-world synthesizability and race-condition awareness.