Configurable APB Memory-Mapped Register Bank with Masking

RTL Problems / Level 6 · Advanced RTL & Protocol Design

What You Will Learn

By solving Configurable APB Memory-Mapped Register Bank with Masking, you will acquire core industry skills:

• Synthesizable hardware modeling in standard Verilog-2001 / SystemVerilog.
• Correct handling of interface port contracts, edge-triggered clocks, and active-low/high resets.
• Simulation waveform interpretation and debugging using timing diagrams (VCD traces).
• Architectural avoidance of timing violations, glitching hazards, and synthesis warnings.

Problem Statement & Requirements

Design a production-grade APB register bank featuring control, status, scratchpad, and interrupt-enable registers with read-only protections.

Hardware design teams at leading semiconductor firms evaluate these exact port contracts, race-condition assertions, and corner cases during technical design reviews and ASIC engineer interviews.

Port List & Interface Timing

The hidden testbench instantiates top_module. Module port names and bit-widths must match the interface contract exactly:

Timing Constraints & Synthesizable RTL Rules

Architectural Deep Dive & Implementation Walkthrough

Common RTL Designer Pitfalls

Silicon & Hardware Engineering Notes

Starter RTL Code

module top_module (
  input  wire        PCLK,
  input  wire        PRESETn,
  input  wire        PSEL,
  input  wire        PENABLE,
  input  wire        PWRITE,
  input  wire [7:0]  PADDR,
  input  wire [31:0] PWDATA,
  output reg  [31:0] PRDATA,
  output wire        PREADY,
  output reg         PSLVERR,
  input  wire [31:0] ext_status,
  output reg  [31:0] ctrl_out,
  output reg  [31:0] ien_out
);

  // Address Map:
  // 0x00: CTRL    (R/W, reset=0x00000000) -> drives ctrl_out

Verified Reference Solution

module top_module (
  input  wire        PCLK,
  input  wire        PRESETn,
  input  wire        PSEL,
  input  wire        PENABLE,
  input  wire        PWRITE,
  input  wire [7:0]  PADDR,
  input  wire [31:0] PWDATA,
  output reg  [31:0] PRDATA,
  output wire        PREADY,
  output reg         PSLVERR,
  input  wire [31:0] ext_status,
  output reg  [31:0] ctrl_out,
  output reg  [31:0] ien_out
);

  assign PREADY = 1'b1;
  reg [31:0] scratch_reg;

  wire wr_en = PSEL && PENABLE && PWRITE;
  wire rd_en = PSEL && PENABLE && !PWRITE;

  always @(posedge PCLK or negedge PRESETn) begin
    if (!PRESETn) begin
      ctrl_out    <= 32'h00000000;
      ien_out     <= 32'h00000000;
      scratch_reg <= 32'hA5A50001;
      PRDATA      <= 32'h00000000;
      PSLVERR     <= 1'b0;
    end else begin
      PSLVERR <= 1'b0;
      if (wr_en) begin
        case (PADDR)
          8'h00: ctrl_out    <= PWDATA;
          8'h04: ; // Status register is Read-Only; writes ignored without error or with error per design
          8'h08: scratch_reg <= PWDATA;
          8'h0C: ien_out     <= PWDATA;
          default: PSLVERR   <= 1'b1;
        endcase
      end

      if (rd_en) begin
        case (PADDR)
          8'h00: PRDATA <= ctrl_out;
          8'h04: PRDATA <= ext_status;
          8'h08: PRDATA <= scratch_reg;
          8'h0C: PRDATA <= ien_out;
          default: begin
            PRDATA  <= 32'h00000000;
            PSLVERR <= 1'b1;
          end
        endcase
      end
    end
  end

endmodule

Related RTL Problems in Level 6

• Manchester Encoder — Combine a data bit with the clock to produce a Manchester-encoded line signal — the self-clocking encoding used in classic Ethernet and RFID.
• Manchester Decoder — Recover the original data bit from a Manchester-encoded line signal — the exact inverse of the Manchester Encoder problem.
• Quadrature Rotary Encoder Decoder — Decode the two-phase A/B signal from a real rotary knob or mouse wheel into a direction and position count — sample B on every rising edge of A.

Frequently Asked Questions