AXI4-Lite Write Channel FSM

Verilog problems / Protocols & Interfaces

What you must build

Accept an address+data write beat, then hold the response channel until the master acknowledges — the handshake FSM behind every AXI4-Lite peripheral.

Engineers use “AXI4-Lite Write Channel FSM” as a building block in protocols & interfaces. Interviewers ask for the same ports and the same corner cases this judge covers. Completing it in the browser is the same skill as writing synthesizable RTL at work, minus the EDA license.

Port contract

The judge instantiates exactly these ports. Extra ports or a different module name fail to elaborate.

How to approach this kata

This is a hard kata. Sketch the state bits and the illegal overlaps (full/empty, wrap, simultaneous enable) on paper first. A design that “usually works” in your head will fail a directed corner in the hidden tests.

Hidden tests instantiate top_module, drive the ports, and compare every sample against a golden model. They do not grade coding style. They do grade X/Z, off-by-one counters, and ignoring enables. Sign in only when you want the run saved on the leaderboard — the specification below is public.

Starter shape

Copy this skeleton into the editor (or press Reset starter). Fill the body; do not rename the module.

module top_module(
  input  clk,
  input  rst,
  input  awvalid,
  output reg awready,
  input  wvalid,
  output reg wready,
  output reg bvalid,
  input  bready
);

  // Your code here — IDLE: accept awvalid&&wvalid for 1 cycle (awready=wready=1), move to RESP.

Why this shows up in interviews

AXI4-Lite Write Channel FSM sits under Protocols &amp; Interfaces (sequential, protocol, amba, fsm). Concept: Once awready / wready pulse to accept an address+data beat, the FSM must drop them back to 0 before moving into the response phase — leaving them asserted through RESP would tell the master it can send a second write before the first one's response ( bvalid / bready ) has even completed, which is a real AXI protocol violation that breaks ordering guarantees the whole bus depends on. Forgetting exactly that one deassertion ( awready<=0; wready<=0; ) when entering RESP is an easy line to drop and a serious one to miss.

A passing solution is synthesizable intent: no delays in the DUT, no initial blocks inside top_module, and no reference to testbench tasks. Use blocking assignments only in combinational always blocks; use non-blocking for registers clocked by clk.

Related problems

• CRC-8 Generator (poly 0x07) — Compute an 8-bit CRC over a byte using the classic 0x07 polynomial (CRC-8-CCITT) — the same bit-serial algorithm behind this catalog's CRC-4, scaled up to a full byte.
• SPI Mode Selector (CPOL/CPHA) — Decode SPI's 4 clocking modes from CPOL and CPHA into the two facts a controller actually needs: what the clock idles at, and which edge samples data.
• APB Slave Register Interface — A minimal AMBA APB slave: 4 registers, zero wait states — and the two-phase setup/access handshake that decides exactly when a write is allowed to land.
• AXI4-Lite Read Channel FSM — The read-side twin of this catalog's AXI4-Lite write FSM: accept an address, then hold the data response until the master accepts it.

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