Burst-Aware AXI4 Read Transaction Controller

RTL Problems / Level 6 · Advanced RTL & Protocol Design

What You Will Learn

By solving Burst-Aware AXI4 Read Transaction Controller, you will acquire core industry skills:

• Synthesizable hardware modeling in standard Verilog-2001 / SystemVerilog.
• Correct handling of interface port contracts, edge-triggered clocks, and active-low/high resets.
• Simulation waveform interpretation and debugging using timing diagrams (VCD traces).
• Architectural avoidance of timing violations, glitching hazards, and synthesis warnings.

Problem Statement & Requirements

Implement an AXI4 read master controller handling address issue, multi-beat read streaming, RLAST tracking, and backpressure.

Hardware design teams at leading semiconductor firms evaluate these exact port contracts, race-condition assertions, and corner cases during technical design reviews and ASIC engineer interviews.

Port List & Interface Timing

The hidden testbench instantiates top_module. Module port names and bit-widths must match the interface contract exactly:

Timing Constraints & Synthesizable RTL Rules

Architectural Deep Dive & Implementation Walkthrough

Common RTL Designer Pitfalls

Silicon & Hardware Engineering Notes

Starter RTL Code

module top_module (
  input  wire        ACLK,
  input  wire        ARESETn,
  input  wire        start_read,
  input  wire [31:0] rd_addr,
  output reg         read_done,
  output reg  [31:0] read_data_out,
  output reg         read_data_valid,
  output reg         read_err,
  output reg         ARVALID,
  input  wire        ARREADY,
  output reg  [31:0] ARADDR,
  input  wire        RVALID,
  output reg         RREADY,
  input  wire [31:0] RDATA,
  input  wire        RLAST,
  input  wire [1:0]  RRESP
);

Verified Reference Solution

module top_module (
  input  wire        ACLK,
  input  wire        ARESETn,
  input  wire        start_read,
  input  wire [31:0] rd_addr,
  output reg         read_done,
  output reg  [31:0] read_data_out,
  output reg         read_data_valid,
  output reg         read_err,
  output reg         ARVALID,
  input  wire        ARREADY,
  output reg  [31:0] ARADDR,
  input  wire        RVALID,
  output reg         RREADY,
  input  wire [31:0] RDATA,
  input  wire        RLAST,
  input  wire [1:0]  RRESP
);

  reg ar_done;

  always @(posedge ACLK or negedge ARESETn) begin
    if (!ARESETn) begin
      read_done       <= 1'b0;
      read_data_out   <= 32'h0;
      read_data_valid <= 1'b0;
      read_err        <= 1'b0;
      ARVALID         <= 1'b0;
      ARADDR          <= 32'h0;
      RREADY          <= 1'b0;
      ar_done         <= 1'b0;
    end else begin
      read_done       <= 1'b0;
      read_data_valid <= 1'b0;

      // Start Read transaction
      if (start_read && !ARVALID && !ar_done) begin
        ARVALID <= 1'b1;
        ARADDR  <= rd_addr;
        ar_done <= 1'b0;
      end

      // AR Channel handshake
      if (ARVALID && ARREADY) begin
        ARVALID <= 1'b0;
        ar_done <= 1'b1;
        RREADY  <= 1'b1; // Ready to receive read beats
      end

      // R Channel beats
      if (RREADY && RVALID) begin
        read_data_out   <= RDATA;
        read_data_valid <= 1'b1;
        if (RRESP != 2'b00) begin
          read_err <= 1'b1;
        end
        if (RLAST) begin
          RREADY    <= 1'b0;
          ar_done   <= 1'b0;
          read_done <= 1'b1;
        end
      end
    end
  end

endmodule

Related RTL Problems in Level 6

• Manchester Encoder — Combine a data bit with the clock to produce a Manchester-encoded line signal — the self-clocking encoding used in classic Ethernet and RFID.
• Manchester Decoder — Recover the original data bit from a Manchester-encoded line signal — the exact inverse of the Manchester Encoder problem.
• Quadrature Rotary Encoder Decoder — Decode the two-phase A/B signal from a real rotary knob or mouse wheel into a direction and position count — sample B on every rising edge of A.

Frequently Asked Questions