AXI-Stream Handshake Counter

Verilog problems / Sequential Design

What you must build

Count how many beats have actually transferred across a valid/ready handshake — a transfer only happens when both sides agree, not whenever the source merely asserts valid.

Engineers use “AXI-Stream Handshake Counter” as a building block in sequential design. Interviewers ask for the same ports and the same corner cases this judge covers. Completing it in the browser is the same skill as writing synthesizable RTL at work, minus the EDA license.

Port contract

The judge instantiates exactly these ports. Extra ports or a different module name fail to elaborate.

How to approach this kata

This is an introductory kata. Prefer a clear continuous assignment or a small combinational always block. Name the module top_module and keep the port list identical to the table — the hidden testbench instantiates that name.

Hidden tests instantiate top_module, drive the ports, and compare every sample against a golden model. They do not grade coding style. They do grade X/Z, off-by-one counters, and ignoring enables. Sign in only when you want the run saved on the leaderboard — the specification below is public.

Starter shape

Copy this skeleton into the editor (or press Reset starter). Fill the body; do not rename the module.

module top_module(
  input  clk,
  input  rst,
  input  valid,
  input  ready,
  output reg [7:0] count
);

  // Your code here — increment count only on cycles where valid AND ready are both high.

endmodule

Why this shows up in interviews

AXI-Stream Handshake Counter sits under Sequential Design (sequential, protocol). Concept: In a ready/valid streaming interface, data only moves on a cycle where both valid and ready are high simultaneously; valid alone just means the source has data waiting, and can sit high for many stalled cycles. Counting on valid without gating on ready overcounts every stall as if it were a real transfer.

A passing solution is synthesizable intent: no delays in the DUT, no initial blocks inside top_module, and no reference to testbench tasks. Use blocking assignments only in combinational always blocks; use non-blocking for registers clocked by clk.

Related problems

• D Flip-Flop with Asynchronous Reset — Standard D flip-flop with an active-low asynchronous reset. Reset clears q immediately, without waiting for a clock edge.
• 4-Bit Shift Register (SIPO) — Serial-in, parallel-out shift register. Each clock, shift left and load sin into the LSB. Sync active-high reset clears q.
• JK Flip-Flop — The flip-flop with no forbidden state: j=k=1 toggles instead of racing. Classic building block for counters.
• 4-Bit Up/Down Counter — A synchronous counter that increments or decrements each clock edge depending on a direction input, with a synchronous reset.

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