AXI-Stream Packet Counter

Verilog problems / Protocols & Interfaces

What you must build

Count completed packets on an AXI-Stream by watching tlast — but only when a beat is actually accepted, not just whenever tlast happens to be asserted.

Engineers use “AXI-Stream Packet Counter” as a building block in protocols & interfaces. Interviewers ask for the same ports and the same corner cases this judge covers. Completing it in the browser is the same skill as writing synthesizable RTL at work, minus the EDA license.

Port contract

The judge instantiates exactly these ports. Extra ports or a different module name fail to elaborate.

How to approach this kata

This is an introductory kata. Prefer a clear continuous assignment or a small combinational always block. Name the module top_module and keep the port list identical to the table — the hidden testbench instantiates that name.

Hidden tests instantiate top_module, drive the ports, and compare every sample against a golden model. They do not grade coding style. They do grade X/Z, off-by-one counters, and ignoring enables. Sign in only when you want the run saved on the leaderboard — the specification below is public.

Starter shape

Copy this skeleton into the editor (or press Reset starter). Fill the body; do not rename the module.

module top_module(
  input  clk,
  input  rst,
  input  tvalid,
  input  tready,
  input  tlast,
  output reg [7:0] packet_count
);

  // Your code here — increment only when tvalid && tready && tlast (a real accepted beat that's also the last one).

endmodule

Why this shows up in interviews

AXI-Stream Packet Counter sits under Protocols &amp; Interfaces (sequential, protocol, amba). Concept: On AXI-Stream, a beat only really transfers when BOTH tvalid and tready are high that cycle — tlast alone means nothing if the receiver isn't ready to accept it: if(tvalid && tready && tlast) packet_count<=packet_count+1 . Counting on tlast alone, without the handshake qualifier, over-counts every time the last beat of a packet happens to coincide with backpressure ( tready=0 ) — the packet hasn't actually been transferred yet, but the counter thinks it has, and then counts it again once the real handshake finally completes.

A passing solution is synthesizable intent: no delays in the DUT, no initial blocks inside top_module, and no reference to testbench tasks. Use blocking assignments only in combinational always blocks; use non-blocking for registers clocked by clk.

Related problems

• CRC-8 Generator (poly 0x07) — Compute an 8-bit CRC over a byte using the classic 0x07 polynomial (CRC-8-CCITT) — the same bit-serial algorithm behind this catalog's CRC-4, scaled up to a full byte.
• SPI Mode Selector (CPOL/CPHA) — Decode SPI's 4 clocking modes from CPOL and CPHA into the two facts a controller actually needs: what the clock idles at, and which edge samples data.
• APB Slave Register Interface — A minimal AMBA APB slave: 4 registers, zero wait states — and the two-phase setup/access handshake that decides exactly when a write is allowed to land.
• AXI4-Lite Write Channel FSM — Accept an address+data write beat, then hold the response channel until the master acknowledges — the handshake FSM behind every AXI4-Lite peripheral.

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